LTC1750IFW Linear Technology, LTC1750IFW Datasheet - Page 15

• Manufacturer Part Number: LTC1750IFW
• Description: IC ADC 14BIT 80MSPS SMPL 48TSSOP
• Manufacturer: Linear Technology

Specifications of LTC1750IFW

• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.69W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Input Range
The LTC1750 performance may be optimized by adjusting
the ADC’s input range to meet the requirements of the
application. For lower input frequency applications
(<80MHz), the highest input range of 1.125V (2.25V) will
provide the best SNR while maintaining excellent SFDR.
For higher input frequencies (>80MHz), a lower input
range will provide better SFDR performance with a reduc-
tion in SNR.
The input range of the ADC is determined as V
where V
Reference Operation section) and A
Table 1
PGA
0
1
0
1
0
1
5V
0.1 F
Figure 6b. 2V Range ADC with External Reference
REF
V
= V
= V
= GND
= GND
0.7V < V
0.7V < V
SENSE
4
is the reference voltage (described in the
DD
DD
LT1790-1.25
SENSE
SENSE
Figure 6a. 2V Range ADC
1, 2
10k
10k
U
2V
1V
< 1.125V
< 1.125V
6
U
SENSE
4.7 F
1 F
1 F
2.5k
V
CM
INPUT RANGE
2.25V
1.35V
1.4V
0.84V
2 V
Peak-to-Peak Differential
1.2 V
Peak-to-Peak Differential
2V
LTC1750
10k
W
P-P
1750 F06a
SENSE
P-P
P-P
P-P
PGA
SENSE
Differential
Differential
Differential
Differential
SENSE
4.7 F
1 F
V
is the effective
CM
U
LTC1750
REF
1750 F06b
/A
PGA
COMMENTS
Best Noise, SNR = 75.5dB. Good SFDR, >82dB Up to 100MHz
Improved High Frequency Distortion. SNR = 73dB. SFDR > 80dB Up to 250MHz
Reduced Internal Reference Mode with PGA = 0. Provides Similar Input Range as
V
Smallest Possible Input Span. Useful for Improved Distortion at Very High
Frequencies, But with Reduced Noise Performance. SNR = 69dB
Adjustable Input Range with Better Noise Performance. SNR = 75.5dB with
V
Adjustable Input Range with Better High Frequency Distortion. SNR = 73dB with
V
SENSE
SENSE
SENSE
,
= V
= 1.125V, SNR = 71.4dB with V
= 1.125V, SNR = 69dB with V
PGA gain. Table 1 shows the input range of the ADC versus
the state of the two pins, PGA and SENSE.
Driving the Encode Inputs
The noise performance of the LTC1750 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
3. If the ADC is clocked with a sinusoidal signal, filter the
4. Balance the capacitance and series resistance at both
The encode inputs have a common mode range of 1.8V to
V
single-ended drive.
DD
DD
coupled use a higher turns ratio to increase the
amplitude.
encode signal to reduce wideband noise.
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
. Each input may be driven from ground to V
and PGA = 0 But with Worse Noise. SNR = 71.4dB
SENSE
SENSE
= 0.7V
= 0.7V
LTC1750
15
DD
1750f
for