LTC1750 LINER [Linear Technology], LTC1750 Datasheet
LTC1750
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LTC1750 Summary of contents
Page 1
... Input Range) optimized with the on-chip PGA sample-and-hold circuit P-P and flexible reference circuitry. The LTC1750 has a highly linear sample-and-hold circuit with a bandwidth of 500MHz. The SFDR is 82dB with an input frequency of 250MHz. Ultralow jitter of 0.12ps allows undersampling of IF frequencies with minimal degradation in SNR. DC specs include 3LSB INL and no missing codes ...
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... Digital Output Voltage ................. – 0. OGND Voltage ..............................................– 0. Power Dissipation ............................................ 2000mW Operating Temperature Range LTC1750C ............................................... LTC1750I ............................................ – Storage Temperature Range ................. – 150 C Lead Temperature (Soldering, 10 sec).................. 300 VERTER CHARACTERISTICS temperature range, otherwise specifications are at T ...
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... Input Signal (PGA = 2.52MHz 5.2MHz (PGA = 0) IN1 IN2 f = 2.52MHz 5.2MHz (PGA = 1) IN1 IN2 SOURCE (Note 5) CONDITIONS OUT OUT 4.75V V 5.25V DD 1mA I 1mA OUT LTC1750 = V DD MIN TYP MAX 75.5 73.0 73 75.3 72.9 74.6 70 72 ...
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... LTC1750 U U DIGITAL I PUTS A D DIGITAL OUTPUTS operating temperature range, otherwise specifications are at T SYMBOL PARAMETER V High Level Input Voltage IH V Low Level Input Voltage IL I Digital Input Current IN C Digital Input Capacitance IN V High Level Output Voltage OH V Low Level Output Voltage ...
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... FREQUENCY (MHz) LTC1750 = 5V 80MHz, differential ENC/ENC = 2V SAMPLE 8192 Point FFT 15.2MHz, IN –1dB, PGA = 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 – ...
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... LTC1750 W U TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT 30.2MHz, IN –10dB, PGA = 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) 1750 G07 8192 Point FFT 70.2MHz, IN –10dB, PGA = 0 0 –10 – ...
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... INPUT LEVEL (dBFS) 1750 G23 LTC1750 8192 Point 2-Tone FFT 26.4MHz and 27.5MHz, IN –7dB Each Tone, PGA = 1 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 ...
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... LTC1750 W U TYPICAL PERFOR A CE CHARACTERISTICS SNR vs Input Frequency and Amplitude, PGA = 1 74 –20dB 73 72 –10dB 71 –1dB 400 500 100 200 300 INPUT FREQUENCY (MHz) 1750 G25 SFDR and SNR vs Sample Rate, 15.2MHz, –1dB Input 100 ...
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... Positive Supply for the Output Driv- DD ers. Bypass to ground with 0.1 F ceramic chip capacitor. D4-D6 (Pins 33 to 35): Digital Outputs. D7-D10 (Pins 39 to 42): Digital Outputs. D11-D13 (Pins 44 to 46): Digital Outputs. OF (Pin 48): Over/Under Flow Output. High when an over or under flow has occurred. LTC1750 /PGA REF 1750f 9 ...
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... LTC1750 DIAGRA • N ANALOG INPUT ENC t 7 DATA t 6 CLKOUT APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output ...
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... SNR JITTER CONVERTER OPERATION The LTC1750 is a CMOS pipelined multistep converter with a front-end PGA. The converter has four pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later, see the Timing Diagram section. The analog input is differential for improved common mode noise immunity and to maximize the input range ...
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... SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC1750 CMOS differential sample-and-hold. The differential ana- log inputs are sampled directly onto sampling capacitors (C ) through NMOS switches ...
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... A balanced input drive will minimize even order harmonics that are due to nonlinear behavior of the input drive circuits and the S/H circuit. The S/H circuit of the LTC1750 is a switched capacitor circuit (Figure 2). The input drive circuitry will see a sampling glitch at the start of the sampling period, when ENC/ENC falls ...
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... This however will raise the noise contributed by the op amps. Reference Operation Figure 5 shows the LTC1750 equivalent reference circuitry consisting bandgap reference, a 3-to-1 switch, a switch control circuit and a difference amplifier. The 2V bandgap reference serves two functions. First ...
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... PGA gain. Table 1 shows the input range of the ADC versus the state of the two pins, PGA and SENSE. Driving the Encode Inputs The noise performance of the LTC1750 can depend on the encode signal quality as much as on the analog input. The ENC/ENC inputs are intended to be driven differentially, ...
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... At sample rates slower than 80Msps the duty cycle can vary from 50% as long as each half cycle is at least 6ns. The lower limit of the LTC1750 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on ...
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... The logic DD outputs will swing between OGND and OV GROUNDING AND BYPASSING The LTC1750 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an inter- nal ground plane is recommended. The pinout of the LTC1750 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized ...
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... ADC OGND (Pin 38). HEAT TRANSFER Most of the heat generated by the LTC1750 is transferred from the die through the package leads onto the printed circuit board. In particular, ground pins 12, 13, 36 and 37 are fused to the die attach pad. These pins have the lowest thermal resistance between the die and the outside envi- ronment ...
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... BSC 3. DRAWING NOT TO SCALE * DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE ** DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE LTC1750 12.4 – 12.6* (.488 – .496) 1.20 (.0473) MAX 0.17 – 0.27 0.05 – ...
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... Pin Compatible with the LTC1742, LTC1744, LTC1748 Pin Compatible with the LTC1741, LTC1743, LTC1745 Pin Compatible with the LTC1742, LTC1744, LTC1746 Pin Compatible with the LTC1750 Rail-to-Rail Input and Output DC to 3GHz, 17dBm IIP3, Integrated LO Buffer 1.5GHz to 2.5GHz, 21.5dBm IIP3, Integrated LO Quadrature Generator ...