LTC1275ACSW Linear Technology, LTC1275ACSW Datasheet - Page 9

• Manufacturer Part Number: LTC1275ACSW
• Description: IC A/D CONV 12BIT SAMPLNG 24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1275ACSW

• Number Of Bits: 12
• Sampling Rate (per Second): 300k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 75mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FU TIO AL BLOCK DIAGRA
PI
V
LTC1276. Bypass to AGND with 0.1µF ceramic.
NC (Pin 23): No Connection for LTC1273.
Table 1. Data Bus Output, CS and RD = LOW
*D11...D0/8 are the ADC data output pins.
TEST CIRCUITS
MNEMONIC*
HBEN = LOW
HBEN = HIGH
DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
SS
DBN
U
U
(Pin 23): Negative Supply. – 5V for LTC1275/
FU
A) HIGH-Z TO V
AND V
U
3k
U
C
DGND
OL
TI
Load Circuits for Access Time
TO V
O
OH
Pin 4
DB11
DB11
OH
V
D11
REF(OUT)
(t
U
3
(t
)
6
S
)
C
A
L
IN
DB10
DB10
Pin 5
D10
REFERENCE
SAMPLE
2.42V
HOLD
DBN
Pin 6
DB9
DB9
D9
C
SAMPLE
B) HIGH-Z TO V
AND V
AGND
CAPACITIVE
12-BIT
Pin 7
OH
DB8
5V
DB8
DAC
D8
W
TO V
3k
1273/75/76 • TA07
DGND
DGND
C
OL
L
OL
(t
3
(t
)
Pin 8
COMPARATOR
LOW
DB7
SAMPLE
6
D7
)
INTERNAL
–
+
CLOCK
12
V
(10µF tantalum in parallel with 0.1µF ceramic).
APPROXIMATION
Pin 9
LOW
DB6
SUCCESSIVE
DD
D6
DBN
REGISTER
CONTROL
(Pin 24): Positive Supply, 5V. Bypass to AGND
LOGIC
Pin 10
LOW
DB5
D5
A) V
V
DD
3k
Load Circuits for Output Float Delay
OH
12
DGND
TO HIGH-Z
V
Pin 11
LOW
SS
DB4
D4
(NC ON LTC1273)
LATCHES
OUTPUT
LTC1275/LTC1276
10pF
Pin 13
D3/11
DB11
DB3
LTC1273/75/76 • FBD
•
•
•
D11
D0/8
BUSY
CS
RD
HBEN
Pin 14
D2/10
DB10
DB2
DBN
B) V
Pin 15
LTC1273
D1/9
DB1
DB9
OL
TO HIGH-Z
5V
1273/75/76 • TA08
3k
DGND
10pF
Pin 16
D0/8
DB0
DB8
127356fa
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