LTC1275ACSW Linear Technology, LTC1275ACSW Datasheet - Page 10

• Manufacturer Part Number: LTC1275ACSW
• Description: IC A/D CONV 12BIT SAMPLNG 24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1275ACSW

• Number Of Bits: 12
• Sampling Rate (per Second): 300k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 75mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1273
LTC1275/LTC1276
A
CONVERSION DETAILS
The LTC1273/LTC1275/LTC1276 use a successive ap-
proximation algorithm and an internal sample-and-hold
circuit to convert an analog signal to a 12-bit parallel or
2-byte output. The ADCs are complete with a precision
reference and an internal clock. The control logic provides
easy interface to microprocessors and DSPs. (Please refer
to the Digital Interface section for the data format.)
Conversion start is controlled by the CS, RD and HBEN
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset and the three-state data
outputs are enabled. Once a conversion cycle has begun
it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
capacitor during the acquire phase, and the comparator
offset is nulled by the feedback switch. In this acquire
phase, a minimum delay of 600ns will provide enough
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
compare mode. The input switch switches C
ground, injecting the analog input charge onto the sum-
ming junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
10
PPLICATI
A
IN
SAMPLE
HOLD
IN
C
SAMPLE
O
C
V
input connects to the sample-and-hold
DAC
DAC
U
Figure 1. A
S
DAC
I FOR ATIO
U
IN
Input
SAMPLE
–
+
LTC1273/75/76 • F01
W
COMPARATOR
SI
SAMPLE
12-BIT
LATCH
U
S
A
R
to
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the A
data word) which represent the A
12-bit output latches.
DYNAMIC PERFORMANCE
The LTC1273/LTC1275/LTC1276 have an exceptionally
high speed sampling capability. FFT (Fast Fourier Trans-
form) test techniques are used to characterize the ADC’s
frequency response, distortion and noise at the rated
throughput. By applying a low distortion sine wave and
analyzing the digital output using an FFT algorithm, the
ADC’s spectral content can be examined for frequencies
outside the fundamental. Figure 2 shows a typical LTC1275
FFT plot.
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with
a 300kHz sampling rate and a 29kHz input. The dynamic
performance is excellent for input frequencies up to the
Nyquist limit of 150kHz.
Figure 2. LTC1275 Nonaveraged, 1024 Point FFT Plot
–100
–120
–40
–60
–20
–80
0
0
IN
20
input charge. The SAR contents (a 12-bit
40
FREQUENCY (kHz)
60
80
f
f
100
SAMPLE
IN
= 29.37kHz
120
IN
LTC1273/75/76 • F02
= 300kHz
are loaded into the
140
160
127356fa