LTC1275ACSW Linear Technology, LTC1275ACSW Datasheet - Page 19

• Manufacturer Part Number: LTC1275ACSW
• Description: IC A/D CONV 12BIT SAMPLNG 24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1275ACSW

• Number Of Bits: 12
• Sampling Rate (per Second): 300k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 75mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

A
MC68000 Microprocessor
Figure 18 shows a typical interface for the MC68000. The
LTC1273 is operating in the Slow Memory Mode. Assum-
ing the LTC1273 is located at address C000, then the
following single 16-bit MOVE instruction both starts a
conversion and reads the conversion result:
At the beginning of the instruction cycle when the ADC
address is selected, BUSY and CS assert DTACK so that
the MC68000 is forced into a WAIT state. At the end of
conversion, BUSY returns high and the conversion result
is placed in the D0 register of the microprocessor.
TMS320C25
Figure 17 shows an interface between the LTC1273 and
the TMS320C25.
The W/R signal of the DSP initiates a conversion and
conversion results are read from the LTC1273 using the
following instruction:
where D is Data Memory Address and PA is the PORT
ADDRESS.
PPLICATI
ADDITIONAL PINS OMITTED FOR CLARITY
TMS320C25
Move.W $C000,D0
IN
READY
R/W
A16
D16
D0
A1
IS
Figure 17. TMS320C25 Interface
D, PA
O
U
S
ADDRESS BUS
EN
DATA BUS
I FOR ATIO
U
ADDRESS
DECODE
W
CS
BUSY
RD
D11
D0/8
LTC1273/75/76
LTC1273/75/76 • F17
U
HBEN
8085A/Z80 Microprocessor
Figure 19 shows an LTC1273 interface for the Z80/8085A.
The LTC1273 is operating in the Slow Memory Mode and
a two byte read is required. Not shown in the figure is the
8-bit latch required to demultiplex the 8085A common
address/data bus. A0 is used to assert HBEN so that an
even address (HBEN = LOW) to the LTC1273 will start a
conversion and read the low data byte. An odd address
(HBEN = HIGH) will read the high data byte. This is
accomplished with the single 16-bit LOAD instruction
below.
ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
MC68000
8085A
For the 8085A
For the Z80
Z80
DTACK
MREQ
WAIT
R/W
A23
D11
A15
AS
D0
A1
RD
D7
D0
A0
Figure 19. 8085A and Z80 Interface
Figure 18. MC68000 Interface
ADDRESS BUS
LTC1275/LTC1276
EN
ADDRESS BUS
EN
DATA BUS
DATA BUS
ADDRESS
DECODE
ADDRESS
DECODE
LHLD (B000)
LDHL, (B000)
LTC1273
CS
BUSY
RD
D11
D0/8
LTC1273/75/76
CS
BUSY
RD
D7
D0/8
LTC1273/75/76
LTC1273/75/76 • F18
LTC1273/75/76 • F19
HBEN
A0
HBEN
19
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