LTC2351HUH-12#PBF Linear Technology, LTC2351HUH-12#PBF Datasheet - Page 5

• Manufacturer Part Number: LTC2351HUH-12#PBF
• Description: IC ADC 12BIT 1.5MSPS 32-QFN
• Manufacturer: Linear Technology

Specifications of LTC2351HUH-12#PBF

• Number Of Bits: 12
• Sampling Rate (per Second): 1.5M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 16.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above V
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
Note 4: Offset and range specifi cations apply for a single-ended CH0
– CH5
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defi ned as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band. Linearity is tested for CH0 only.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defi ned for the voltage difference
between CHx
Note 9: The absolute voltage at CHx
range, otherwise specifi cations are at T
SYMBOL
t
t
t
9
10
11
+
input with CH0
+
and CHx
PARAMETER
SCK↑ to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
Settling Time After Sleep-to-Wake Transition
–
–
– CH5
, x = 0 to 5.
–
grounded and using the internal 2.5V
+
and CHx
DD
without latchup.
A
–
= 25°C. V
must be within this range.
DD
DD
The
, they will be
= 3V.
l
denotes the specifi cations which apply over the full operating temperature
+
CONDITIONS
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 14)
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
96th rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The conversion process takes 16 clocks for each channel that is
enabled, up to 96 clocks for all 6 channels.
P-P
MIN
2
input sine wave.
LTC2351-12
TYP
2
MAX
6
235112fa
UNITS
5
ms
ns
ns