LTC2351HUH-12#PBF Linear Technology, LTC2351HUH-12#PBF Datasheet - Page 18

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LTC2351HUH-12#PBF

Manufacturer Part Number
LTC2351HUH-12#PBF
Description
IC ADC 12BIT 1.5MSPS 32-QFN
Manufacturer
Linear Technology
Datasheet

Specifications of LTC2351HUH-12#PBF

Number Of Bits
12
Sampling Rate (per Second)
1.5M
Data Interface
Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
16.5mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
32-WFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC2351HUH-12#PBFLTC2351HUH-12
Manufacturer:
LT
Quantity:
10 000
APPLICATIONS INFORMATION
LTC2351-12
the rising edge of CONV. The six or fewer 12-bit words are
separated by two don’t care bits and two clock cycles in
high impedance mode. Please note the delay specifi cation
from SCK to a valid SDO. SDO is always guaranteed to
be valid by the next rising edge of SCK. The 16 – 96-bit
output data stream is compatible with the 16-bit or 32-bit
serial port of most processors.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC2351-12, a printed circuit board
with ground plane is required. Layout for the printed circuit
board should ensure that digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track. If optimum phase match between the
inputs is desired, the length of the twelve input wires of
the six input channels should be kept matched. But each
pair of input wires to the six input channels should be
kept separated by a ground trace to avoid high frequency
crosstalk between channels.
High quality tantalum and ceramic bypass capacitors
should be used at the V
in the Block Diagram on the fi rst page of this data sheet.
18
Figure 6. Recommended Layout
OV
CC
0.1μF, 0402
V
DD
REF
10μF, 0805
, V
BYPASS,
BYPASS,
DD
and V
REF
V
0.1μF, 0402
V
0.1μF, 0402 AND
10μF, 0805
DD
CC
pins as shown
BYPASS,
BYPASS,
For optimum performance, a 10μF surface mount tantalum
capacitor with a 0.1μF ceramic is recommended for the
V
capacitors such as X5R or X7R may be used. The capaci-
tors must be located as close to the pins as possible. The
traces connecting the pins and the bypass capacitors must
be kept short and should be made as wide as possible. The
V
and the V
should be taken to place the 0.1μF V
capacitor as close to Pins 24 and 25 as possible.
Figure 6 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated at
the LTC2351-12 Exposed Pad. The ground return from the
LTC2351-12 to the power supply should be low impedance
for noise-free operation. The Exposed Pad of the 32-pin
QFN package is also internally tied to the ground pads.
The Exposed Pad should be soldered on the PC board to
reduce ground connection inductance. All ground pins
(GND, DGND, OGND) must be connected directly to the
same ground plane under the LTC2351-12.
HARDWARE INTERFACE TO TMS320C54x
The LTC2351-12 is a serial output ADC whose interface
has been designed for high speed buffered serial ports in
fast digital signal processors (DSPs). Figure 7 shows an
example of this interface using a TMS320C54X.
LTC2351-12
CC
CC
, V
OGND
DGND
CONV
OV
and V
SDO
SCK
DD
DD
3
30
32
1
2
31
Figure 7. DSP Serial Interface to TMS320C54x
REF
and V
DD
3V
CONV
bypass capacitor returns to the ground plane
bypass capacitor returns to the Pin 22. Care
CLK
0V TO 3V LOGIC SWING
REF
pins. Alternatively, 10μF ceramic chip
INTERFACE LINK
3-WIRE SERIAL
5V
CC
and V
B11
B10
DD
V
BFSR
BCLKR
BDR
TMS320C54x
bypass
CC
235112fa
235112 F07

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