LTC1277CSW Linear Technology, LTC1277CSW Datasheet - Page 5

• Manufacturer Part Number: LTC1277CSW
• Description: IC A/D CONV 12BIT W/SHTDN 24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1277CSW

• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 20mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC1277CS

TI I G CHARACTERISTICS
TYPICAL PERFORMANCE CHARACTERISTICS
SYMBOL
t
t
t
The
temperature range; all other limits and typicals T
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together and V
otherwise noted).
Note 3: When these pin voltages are taken below V
mode) or above V
can handle input currents greater than 60mA below V
unipolar mode) or above V
Note 4: When these pin voltages are taken below V
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below V
without latch-up. These pins are not clamped to V
Note 5: V
f
Note 6: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
16
17
18
SAMPLE
–0.50
–1.00
1.00
0.50
W U
●
0
denotes specifications which apply over the full operating
0
Integral Nonlinearity vs
Output Code
= 100ksps, t
f
DD
SAMPLE
512 1024 1536 2048
= 5V (V
PARAMETER
HBEN↓ to Low Byte Data Valid
HBEN↑ to RD↓ Setup Time
RD↑ to HBEN↓ Setup Time
= 100kHz
DD
SS
, they will be clamped by internal diodes. This product
r
OUTPUT CODE
= t
= – 5V for bipolar mode), V
f
= 5ns unless otherwise specified.
DD
LOGIC
without latch-up.
2560 3072 3584 4096
is tied to V
W
LT1274/77 • TPC01
SS
U
DD
(ground for unipolar mode)
in LTC1277 (unless
A
DD
LOGIC
= 25°C.
SS
SS
.
SS
(ground for unipolar
(ground for unipolar
–0.50
–1.00
CONDITIONS
C
(Note 10) (LTC1277 Only)
(Note 10) (LTC1277 Only)
0.50
1.00
= V
(ground for
L
0
= 100pF (LTC1277 Only)
DD
0
Differential Nonlinearity vs
Output Code
f
(Note 5) See Figures 13 to 17.
(LTC1277),
SAMPLE
512 1024 1536 2048
= 100kHz
OUTPUT CODE
Note 8: For LTC1274, bipolar offset is the offset voltage measured from
– 0.5LSB when the output code flickers between 0000 0000 0000 and
1111 1111 1111. For LTC1277, bipolar offset voltage is measured from
– 0.5LSB when the output code flickers between 0111 1111 1111 and
1000 0000 0000.
Note 9: The AC tests apply to bipolar mode only and the S/(N + D) is 71dB
(typ) for unipolar mode at 100kHz input frequency.
Note 10: Guaranteed by design, not subject to test.
Note 11: Recommended operating conditions.
Note 12: A
specified accuracy.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a bit decision point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 400ns after conversion start (i.e., before the first bit decision) or
after BUSY rises (i.e., after the last bit test). See timing diagrams Modes
1a and 1b (Figures 13, 14).
2560 3072 3584 4096
LT1274/77 • TPC02
IN
must not exceed V
12
11
10
9
8
7
6
5
4
3
2
1
0
10k
ENOBs and S/(N + D) vs
Input Frequency
●
●
●
f
LTC1274/LTC1277
DD
SAMPLE
or fall below V
MIN
10
10
= 100kHz
INPUT FREQUENCY (Hz)
100k
FREQUENCY
NYQUIST
TYP
45
SS
by more than 50mV to
MAX
100
LTC1274/77 • TPC03
1M
2M
UNITS
5
74
68
62
56
50
ns
ns
ns