LTC1277CSW Linear Technology, LTC1277CSW Datasheet

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LTC1277CSW

Manufacturer Part Number
LTC1277CSW
Description
IC A/D CONV 12BIT W/SHTDN 24SOIC
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1277CSW

Number Of Bits
12
Sampling Rate (per Second)
100k
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
20mW
Voltage Supply Source
Dual ±
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (0.300", 7.50mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
LTC1277CS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LTC1277CSW
Manufacturer:
LT
Quantity:
135
Part Number:
LTC1277CSW
Manufacturer:
LINEAR/凌特
Quantity:
20 000
FEATURE
A
V
TYPICAL
REF
PPLICATI
Low Power Dissipation: 10mW
Sample Rate: 100ksps
Samples Inputs Beyond Nyquist, 72dB S/(N + D)
and 82dB THD at f
Single Supply 5V or ±5V Operation
Power Shutdown to 1µA in Sleep Mode
180µA Nap Mode (LTC1277) with Instant Wake-Up
Internal Reference Can Be Overdriven
Internal Synchronized Clock
0V to 4.096V or ±2.048V Input Ranges (1mV/LSB)
24-Lead SO Package
Battery-Powered Portable Systems
High Speed Data Acquisition for PCs
Digital Signal Processing
Multiplexed Data Acquisition Systems
Audio and Telecom Processing
Spectrum Analysis
OUTPUT
2.42V
10µF
DIFFERENTIAL INPUTS
+
S
A
O
PPLICATI
(0V TO 4.096V)
Single 5V Supply, 10mW, 100kHz, 12-Bit ADC
PARALLEL
U
IN
8-BIT
ANALOG
BUS
S
0.1µF
= 100kHz
10
11
12
1
2
3
4
5
6
7
8
9
A
A
V
AGND
REFRDY
SLEEP
NAP
D7
D6
D5
D4
DGND
O
IN
IN
REF
+
LTC1277
U
CONVST
V
D2/10
D3/11
BUSY
HBEN
LOGIC
D0/8
D1/9
V
V
RD
CS
DD
SS
24
23
22
21
20
19
18
17
16
15
14
13
µP
CONTROL
LINES
10µF
LTC1274/77 • TA01
OPTIONAL 3V SUPPLY
TO INTERFACE WITH 3V
PROCESSOR
+
D
The LTC
converters which draw only 2mA (typ) from single 5V or
±5V supplies. These easy-to-use devices come complete
with a 2µs sample-and-hold, a precision reference and an
internally trimmed clock. Unipolar and bipolar conversion
modes add to the flexibility of the ADCs.
Two power-down modes are available in the LTC1277. In
Nap mode, the LTC1277 draws only 180µA and the instant
wake-up from Nap mode allows the LTC1277 to be pow-
ered down even during brief inactive periods. In Sleep
mode only 1µA will be drawn. A REFRDY signal is used to
show the ADC is ready to sample after waking up from
Sleep mode. The LTC1274 also provides the Sleep mode
and REFRDY signal.
The A/D converters convert 0V to 4.096V unipolar inputs
from a single 5V supply or ±2.048V bipolar inputs from
±5V supplies.
The LTC1274 has a single-ended input and a 12-bit
parallel data format. The LTC1277 offers a differential
input and a 2-byte read format. The bipolar mode is
formatted as 2’s complement for the LTC1274 and offset
binary for the LTC1277.
5V
, LTC and LT are registered trademarks of Linear Technology Corporation.
ADCs with 1µA Shutdown
ESCRIPTIO
0.1µF
®
1274/LTC1277 are 8µs sampling 12-bit A/D
12-Bit, 10mW, 100ksps
10000
1000
100
10
1
U
0.1
Supply Current vs Sample Rate with
C
REF
LTC1274/LTC1277
= 4.7µF
1
Sleep and Nap Modes
WITHOUT SLEEP OR NAP
NAP = REFRDY
(SLEEP MODE)
NAP = 5V
(SLEEP MODE)
SAMPLE RATE (Hz)
10
100
NAP MODE
1k
LTC1274/77 • TA02
10k
100k
1

Related parts for LTC1277CSW

LTC1277CSW Summary of contents

Page 1

... The LTC1274 has a single-ended input and a 12-bit parallel data format. The LTC1277 offers a differential input and a 2-byte read format. The bipolar mode is formatted as 2’s complement for the LTC1274 and offset binary for the LTC1277. , LTC and LT are registered trademarks of Linear Technology Corporation ...

Page 2

... AGND LTC1274ISW REFRDY SLEEP NAP DGND 24-LEAD PLASTIC SO WIDE T With Internal Reference (Notes 5, 6) CONDITIONS (Note 7) (Note OUT(REF) TOP VIEW ORDER PART NUMBER BUSY LTC1277CSW LTC1277ISW CONVST 7 18 HBEN LOGIC D2/ D3/11 (D11 = MSB) SW PACKAGE = 110°C, θ = 130°C/W ...

Page 3

LOG I PUT (Note 5) SYMBOL PARAMETER V Analog Input Range (Note 10 Analog Input Leakage Current IN C Analog Input Capacitance ACCURACY SYMBOL PARAMETER S/( ...

Page 4

LTC1274/LTC1277 U U DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL PARAMETER I High-Z Output Leakage D11 to D0 High-Z Output Capacitance D11 to D0 Output Source Current SOURCE I Output Sink Current SINK W U ...

Page 5

CHARACTERISTICS SYMBOL PARAMETER t HBEN↓ to Low Byte Data Valid 16 t HBEN↑ to RD↓ Setup Time 17 t RD↑ to HBEN↓ Setup Time 18 ● The denotes specifications which apply over the full operating ...

Page 6

LTC1274/LTC1277 W U TYPICAL PERFORMANCE CHARACTERISTICS S/( Input Frequency and Amplitude 0dB – 20dB – 60dB 100kHz SAMPLE ...

Page 7

W U TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Temperature 3 100kHz SAMPLE 2.5 2.0 1.5 1.0 0 100 125 –55 – TEMPERATURE (°C) LT1274/77 • TPC11 Supply Current vs Supply Voltage 3.0 f ...

Page 8

LTC1274/LTC1277 CTIO S RD (Pin 20): Read Input. This enables the output drivers when CS is low. CS (Pin 21): The Chip Select input must be low for the ADC to recognize CONVST and RD ...

Page 9

W BLOCK DIAGRA REF 2.42V REF REFRDY AGND DGND INTERNAL CLOCK + A IN – REF 2.42V REF REFRDY AGND DGND INTERNAL CLOCK TEST CIRCUITS Load Circuits for Access Timing DBN DBN 3k ...

Page 10

LTC1274/LTC1277 DIAGRA Setup Timing NAP to CONVST Wake-Up Timing (LTC1277) NAP t 3 CONVST U U APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1274/LTC1277 use a successive approximation ...

Page 11

U U APPLICATIONS INFORMATION using an FFT algorithm, the ADCs’ spectral content can be examined for frequencies outside the fundamental. Figures 2a and 2b show typical LTC1274 FFT plots. Signal-to-Noise Ratio The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is ...

Page 12

LTC1274/LTC1277 U U APPLICATIONS INFORMATION quency is shown in Figure 4. The ADCs have good distor- tion performance up to the Nyquist frequency and beyond. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ...

Page 13

PPLICATI S I FOR ATIO + – LTC1277 A /A Input Settling IN IN The input capacitor for the LTC1277 is switched onto the + A input during the sample phase. The voltage on the IN ...

Page 14

LTC1274/LTC1277 PPLICATI S I FOR ATIO Figure 8. For bipolar mode, a 0.1µF ceramic provides adequate bypassing for the V pin. The capacitors must SS be located as close to the pins as possible. The traces ...

Page 15

PPLICATI FOR ATIO DIGITAL INTERFACE The ADCs are designed to interface with microproces- sors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate ...

Page 16

LTC1274/LTC1277 PPLICATI FOR ATIO adjusted before full-scale error. Bipolar offset error ad- justment is achieved by trimming the offset adjust while the input voltage is 0.5LSB below ground. This is done by applying an ...

Page 17

PPLICATI S I FOR ATIO The narrow logic pulse on CONVST ensures that CONVST doesn’t return high during the conversion (see Note 13 following the Timing Characteristics table). In Mode 2 (Figure 15 tied ...

Page 18

LTC1274/LTC1277 PPLICATI S I FOR ATIO HBEN (LTC1277 CONVST BUSY DATA (N – 1) LTC1274 DATA DB11 TO DB0 DATA (N – 1) DATA (N – 1) LTC1277 DATA ...

Page 19

... ADC is ready to do conversions. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ...

Page 20

... Fast, Complete Low Power ADC, 80mV Fast, Complete Wideband ADC, 160mV : 499-3977 3ms (C = 4.7µF) REF ON OFF 0.598 – 0.614* (15.190 – 15.600 NOTE LT/GP 1195 10K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1995 ON LTC1274/77 • F18b 0.394 – 0.419 (10.007 – 10.643) ...

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