LTC1277CSW Linear Technology, LTC1277CSW Datasheet - Page 19

• Manufacturer Part Number: LTC1277CSW
• Description: IC A/D CONV 12BIT W/SHTDN 24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1277CSW

• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 20mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC1277CS

Power Shutdown
The LTC1274/LTC1277 provide shutdown features that
will save power when the ADC is in inactive periods. Both
ADCs have a Sleep mode. To power down the ADCs,
SLEEP (Pin 18 in LTC1274 or Pin 6 in LTC1277) needs to
be driver low. When in Sleep mode, the LTC1274/LTC1277
will not start a conversion even though the CONVST goes
low. The parts draw 1µA. After release from the Sleep
mode, the ADCs need 3ms (4.7µF bypass capacitor on
V
to indicate the ADC is ready to do conversions.
A
REF
PPLICATI
pin) to wake up and a REFRDY signal will go to high
HBEN (LTC1277)
HBEN (LTC1277)
LTC1274 DATA
LTC1277 DATA
RD = CONVST
LTC1274 DATA
LTC1277 DATA
RD = CONVST
CS = 0
BUSY
CS = 0
BUSY
O
U
S
t
5
I FOR ATIO
t
5
t
U
(SAMPLE N)
9
t
(SAMPLE N)
9
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DATA (N – 1)
DB11 TO DB0
DATA (N – 1)
DATA (N – 1)
DB7 TO DB0
DB7 TO DB0
DB11 TO DB0
DATA (N – 1)
t
CONV
t
15
W
t
DB11 TO DB8
DATA (N – 1)
18
t
DB7 TO DB0
t
10
6
DB11 TO DB0
Figure 16. Slow Memory Mode
DATA N
Figure 17. ROM Mode Timing
DATA N
U
t
t
15
CONV
DB11 TO DB8
t
18
DATA N
t
10
t
7
The LTC1277 has an additional Nap mode. When NAP
(Pin 7) is tied low, all the power is off except the internal
reference which is still active and provides 2.42V output
voltage to the other circuitry. In this mode the ADC draws
0.9mW instead of 10mW (for minimum power, the logic
inputs must be within 600mV from the supply rails). The
wake-up time from the power shutdown to active state is
620ns. The typical performance graph on the front page of
this data sheet shows that the power will be reduced
greatly by using the Sleep and Nap modes.
t
7
(SAMPLE N + 1)
(SAMPLE N + 1)
DB11 TO DB0
DB11 TO DB0
DB7 TO DB0
DATA N
DATA N
DATA N
DB11 TO DB0
DATA N
LTC1274/LTC1277
DB11 TO DB8
DATA (N + 1)
DB7 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB8
DATA (N + 1)
LTC1274/77 • F16
LTC1274/77 • F17
19