LTC2424IG Linear Technology, LTC2424IG Datasheet - Page 27

• Manufacturer Part Number: LTC2424IG
• Description: IC ADC 20BIT 4CH MICROPWR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC2424IG

• Number Of Bits: 20
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
nonlinearity of the multiplexer switch is seen in the
overall transfer characteristic.
In addition to the input current spikes, the input ESD
protection diodes have a temperature dependent leakage
current. This leakage current, nominally 1nA ( 10nA
max), results in a fixed offset shift of 10 V for a 10k source
resistance.
Reference Current (V
Similar to the analog input, the reference input has a
dynamic input current. This current has negligible effect
on the offset. However, the reference current at V
is similar to the input current at full-scale. For large values
of reference capacitance (C
Figure 24. Full-Scale Error vs R
–15
–20
–25
–35
–10
–30
–5
35
30
25
20
15
10
Figure 23. Offset vs R
5
0
5
0
0
0
V
V
V
T
A
CC
REF
IN
= 25 C
= 0V
= 5V
= 5V
200
200
C
C
C
C
C
C
C
C
C
C
C
C
U
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 22 F
= 10 F
= 1 F
= 0.1 F
= 0.01 F
= 0.001 F
= 22 F
= 10 F
= 1 F
= 0.1 F
= 0.01 F
= 0.001 F
REF
400
400
R
R
INFORMATION
SOURCE
SOURCE
)
U
VREF
600
600
( )
( )
SOURCE
> 0.01 F), the full-scale
SOURCE
W
V
V
V
T
800
800
A
CC
REF
IN
(Large C)
= 25 C
= 0V
= 5V
24248 F23
= 5V
24248 F24
(Large C)
1000
1000
U
IN
= V
REF
error shift is 0.03ppm/ of external reference resistance
independent of the capacitance at V
the capacitance tied to V
input resistance of up to 80k (20pF parasitic capacitance
at V
Unlike the analog input, the integral nonlinearity of the
device can be degraded with excessive external RC time
constants tied to the reference input. If the capacitance at
node V
can tolerate large external resistances without reduction
in INL, see Figure 27. If the external capacitance is large
(C
0.015ppm/
Figure 28.
VREF
REF
) may be tolerated, see Figure 26.
REF
> 0.01 F), the linearity will be degraded by
Figure 25. Full-Scale Error vs R
Figure 26. Full-Scale Error vs R
–100
–200
–10
500
400
300
200
100
is small (C
60
50
40
30
20
10
0
0
1
0
V
V
V
T
V
V
V
T
independent of capacitance at V
A
A
CC
REF
IN
CC
REF
IN
= 25 C
= 25 C
= 5V
= 5V
= 5V
= 5V
= 5V
= 5V
200
10
C
C
C
C
C
C
VREF
VREF
VREF
VREF
VREF
VREF
RESISTANCE AT V
RESISTANCE AT V
VREF
= 22 F
= 10 F
= 1 F
= 0.1 F
= 0.01 F
= 0.001 F
LTC2424/LTC2428
400
100
REF
C
C
VREF
C
VREF
VREF
< 0.01 F), the reference input
is small (C
= 1000pF
= 0.01 F
= 100pF
600
1k
REF
REF
( )
C
( )
VREF
VREF
VREF
REF
800
10k
= 0pF
VREF
24248 F26
24248 F25
, see Figure 25. If
(Large C)
(Small C)
1000
100k
< 0.01 F), an
REF
27
, see