LTC2424IG Linear Technology, LTC2424IG Datasheet - Page 23

• Manufacturer Part Number: LTC2424IG
• Description: IC ADC 20BIT 4CH MICROPWR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC2424IG

• Number Of Bits: 20
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CSADC. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CSADC. An internal weak pull-up
resistor is active on the SCK pin during the falling edge of
CSADC; therefore, the internal serial clock timing mode is
automatically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CSADC
is HIGH. At any time during the conversion cycle, CSADC
may be pulled LOW in order to monitor the state of the
converter. Once CSADC is pulled LOW, SCK goes LOW
and EOC is output to the SDO pin. EOC = 1 while a
conversion is in progress and EOC = 0 if the device is in the
sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CSADC remains LOW. In order to prevent the
device from exiting the low power sleep state, CSADC
must be pulled HIGH before the first rising edge of SCK. In
the internal SCK timing mode, SCK goes HIGH and the
device begins outputting data at time t
falling edge of CSADC (if EOC = 0) or t
goes LOW (if CSADC is LOW during the falling edge of
EOC). The value of t
internal oscillator (F
by an external oscillator of frequency f
3.6/f
device remains in the sleep state and the power consump-
tion is reduced an order of magnitude. The conversion
result is held in the internal static shift register.
If CSADC remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 24th rising edge of SCK. After the
APPLICATIONS
EOSC
. If CSADC is pulled HIGH before time t
EOCtest
U
0
= logic LOW or HIGH). If F
INFORMATION
U
is 23 s if the device is using its
W
EOCtest
EOSC
EOCtest
EOCtest
, then t
, the first rising
EOCtest
O
U
after EOC
after the
is driven
EOCtest
, the
is
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
While operating in the internal serial clock mode, the SCK
output of the ADC may be used as the multiplexer clock
(CLK). D
edge of CLK. As shown in Figure 16, the multiplexer
channel is selected by serial shifting a 4-bit word into the
D
bit which must be HIGH in order to program a channel. The
next three bits determine which channel is selected, see
Table 3. On the rising edge of CSADC (falling edge of
CSMUX), the new channel is selected and will be valid for
the next conversion. If D
output state, the previous channel selection remains valid.
Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first and 24th
rising edge of SCK, see Figure 17. On the rising edge of
CSADC, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 24 bits of output data, aborting
an invalid conversion cycle, or synchronizing the start of
a conversion. If CSADC is pulled HIGH while the con-
verter is driving SCK LOW, the internal pull-up is not
available to restore SCK to a logic HIGH state. This will
cause the device to exit the internal serial clock mode on
the next falling edge of CSADC. This can be avoided by
adding an external 10k pull-up resistor to the SCK pin or
by never pulling CSADC HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2424/LTC2428’s internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
mode. However, certain applications may require an exter-
nal driver on SCK. If this driver goes Hi-Z after outputting
a LOW signal, the LTC2424/LTC2428’s internal pull-up
remains disabled. Hence, SCK remains LOW. On the next
falling edge of CSADC, the device is switched to the
external SCK timing mode. By adding an external 10k pull-
up resistor to SCK, this pin goes HIGH once the external
driver goes Hi-Z. On the next CSADC falling edge, the
device will remain in the internal SCK timing mode.
IN
pin on the rising edge of CLK. The first bit is an enable
IN
is latched into the multiplexer on the rising
LTC2424/LTC2428
IN
is held LOW during the data
23