MAX1145BEAP+ Maxim Integrated Products, MAX1145BEAP+ Datasheet - Page 11

• Manufacturer Part Number: MAX1145BEAP+
• Description: IC ADC 14BIT 150KSPS 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1145BEAP+

• Number Of Bits: 14
• Sampling Rate (per Second): 150k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 26.4mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Conversion Rate: 150 KSPs
• Resolution: 14 bit
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Snr: 82 dB
• Voltage Reference: 2.048 V
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Power Dissipation: 640 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5. Internal Clock Mode Timing, Short Acquisition, Bipolar Mode
Figure 6. Internal Clock Mode SSTRB Detailed Timing
In long acquisition mode, SSTRB pulses high for one
clock period after the 15th falling edge of SCLK follow-
ing the start bit. The MSB of the conversion is available
at DOUT on the 16th falling edge of SCLK (Figure 3).
In external clock mode, SSTRB is high impedance
when CS is high (Figure 4). In external clock mode, CS
is normally held low during the entire conversion. If CS
goes high during the conversion SCLK is ignored until
CS goes low. This allows external clock mode to be
used with 8-bit bytes.
In internal clock mode, the MAX1144/MAX1145 generate
their own conversion clock. This frees the microprocessor
from the burden of running the SAR conversion clock,
SSTRB
DOUT
SCLK
DIN
CS
START
SSTRB
14-Bit ADCs, 150ksps, 3.3V Single Supply
1
SCLK
CS
UNI/
BIP
______________________________________________________________________________________
INT/
EXT
t
ACQ
M1
P0 CLOCKED IN
4
M0
P2
t
CSH
P1
Internal Clock
P0
8
t
SSTRB
t
CONV
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
t
CONV
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate up to 4MHz.
SSTRB goes low at the start of the conversion and goes
high when the conversion is complete. SSTRB will be
low for a maximum of 7µs, during which time SCLK
should remain low for best noise performance. An inter-
nal register stores data when the conversion is in
progress. SCLK clocks the data out of the internal stor-
age register at any time after the conversion is complete.
The MSB of the conversion is available at DOUT when
SSTRB goes high. The subsequent 13 falling edges on
SCLK shift the remaining bits out of the internal storage
register (Figure 5). CS does not need to be held low
once a conversion is started.
MSB
B13
9
B12
B2
t
SCK
B1
LSB
B0
21
X
t
CSS
X
24
FILLED WITH
ZEROS
11