MAX1145BEAP+ Maxim Integrated Products, MAX1145BEAP+ Datasheet - Page 10

• Manufacturer Part Number: MAX1145BEAP+
• Description: IC ADC 14BIT 150KSPS 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1145BEAP+

• Number Of Bits: 14
• Sampling Rate (per Second): 150k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 26.4mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Conversion Rate: 150 KSPs
• Resolution: 14 bit
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Snr: 82 dB
• Voltage Reference: 2.048 V
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Power Dissipation: 640 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The user-programmable outputs are set to zero during
power-on reset or when RST goes low. During hardware
or software shutdown, P0, P1, and P2 are unchanged
and remain low-impedance.
Start a conversion by clocking a control byte into the
device’s internal shift register. With CS low, each rising
edge on SCLK clocks a bit from DIN into the
MAX1144/MAX1145’s internal shift register. After CS
goes low or after a conversion or calibration completes,
the first arriving logic “1” is defined as the start bit of
the control byte. Until this first start bit arrives, any num-
ber of logic “0” bits can be clocked into DIN with no
effect. If at any time during acquisition or conversion
CS is brought high and then low again, the part is
placed into a state where it can recognize a new start
bit. If a new start bit occurs before the current conver-
sion is complete, the conversion is aborted and a new
acquisition is initiated.
Figure 4. External Clock Mode SSTRB Detailed Timing
14-Bit ADCs, 150ksps, 3.3V Single Supply
Figure 3. Long Acquisition Mode (32 Clock Cycles) External Clock
10
______________________________________________________________________________________
SSTRB
DOUT
SCLK
DIN
STATE
CS
A/D
SSTRB
SCLK
CS
START
IDLE
1
UNI/
BIP
INT/
EXT
Starting a Conversion
M1
4
M0
t
SDV
ACQUISITION
P2
t
ACQ
P1
P0
8
P1 CLOCKED IN
14
15
The MAX1144/MAX1145 use either the external serial
clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the
MAX1144/MAX1145. Bit 5 (INT/EXT) of the control byte
programs the clock mode.
In external clock mode, the external clock not only
shifts data in and out, but also drives the ADC conver-
sion steps.
In short acquisition mode, SSTRB pulses high for one
clock period after the seventh falling edge of SCLK fol-
lowing the start bit. The MSB of the conversion is avail-
able at DOUT on the eighth falling edge of SCLK
(Figure 2).
t
SSTRB
MSB
B13
B12
B11
Internal and External Clock Modes
CONVERSION
t
SSTRB
B2
B1
29
LSB
B0
X
t
STR
X
32
FILLED WITH
External Clock
ZEROS
IDLE