ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 9

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

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STATIC CONVERTER CHARACTERISTICS
INL
DNL
V
V
PFSE
NFSE
FS_ADJ
NORMAL MODE (non DES) DYNAMIC CONVERTER CHARACTERISTICS
FPBW
B.E.R.
ENOB
SINAD
Symbol
OFF
OFF
Absolute Maximum Ratings
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Converter Electrical Characteristics
The following specifications apply after calibration for V
870mV
Floating, Non-Extended Control Mode, SDR Mode, R
Boldface limits apply for T
Supply Voltage (V
Supply Difference
Voltage on Any Input Pin
(Except V
Voltage on V
(Maintaining Common Mode)
Ground Difference
Input Current at Any Pin
Package Input Current
Power Dissipation at T
ESD Susceptibility
Soldering Temperature, Infrared,
Storage Temperature
_ADJ Input Offset Adjustment Range
|GND - DR GND|
Human Body Model
Machine Model
10 seconds
V
P-P
DR
, C
Integral Non-Linearity
Differential Non-Linearity
Resolution with No Missing Codes
Offset Error
Positive Full-Scale Error
Negative Full-Scale Error
Full-Scale Adjustment Range
Full Power Bandwidth
Bit Error Rate
Gain Flatness
Effective Number of Bits
Signal-to-Noise Plus Distortion Ratio
- V
IN
+, V
L
A
IN
= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f
+, V
IN
(Note
- )
A
IN
(Note
, V
-
DR
Parameter
A
5)
(Note
)
= 85°C
(Note
4)
A
= T
3)
3)
MIN
(Note
(Note
to T
−0.15V to (V
MAX
9)
−65°C to +150°C
9)
. All other limits T
-0.15V to 2.5V
0V to 100 mV
0V to 100 mV
(Note
DC Coupled, 1MHz Sine Wave Over
ranged
DC Coupled, 1MHz Sine Wave Over
ranged
Extended Control Mode
Extended Control Mode
Normal (non DES) Mode
d.c. to 500 MHz
f
f
f
f
f
f
A
IN
IN
IN
IN
IN
IN
+0.15V)
±25 mA
±50 mA
= 50 MHz, V
= 100 MHz, V
= 248 MHz, V
= 50 MHz, V
= 100 MHz, V
= 248 MHz, V
2500V
1,
235°C
EXT
2.0 W
250V
2.2V
A
Note
= V
= 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential.
DR
A
Conditions
= +1.9V
8
= 25°C, unless otherwise noted.
IN
IN
IN
IN
IN
IN
= FSR − 0.5 dB
= FSR − 0.5 dB
Operating Ratings
Soldering
Semiconductor’s Reflow Temperature Profile specifications.
Refer to www.national.com/packaging.
= FSR − 0.5 dB
= FSR − 0.5 dB
= FSR − 0.5 dB
= FSR − 0.5 dB
Ambient Temperature Range
Supply Voltage (V
Driver Supply Voltage (V
Analog Input Common Mode Voltage
V
(Maintaining Common Mode)
Ground Difference
CLK Pins Voltage Range
Differential CLK Amplitude
IN
DC
CLK
+, V
Exposed Pad
(|GND - DR GND|)
, OutV = 1.9V, V
128-Lead
Package
= 500 MHz at 0.5V
IN
LQFP
- Voltage Range
process
Package Thermal Resistance
A
)
IN
(Note
25°C / W
Typical
±0.15
−1.31
-0.45
10
FSR (a.c. coupled) = differential
±0.3
−0.6
±0.5
±45
±20
must
1.7
7.5
7.5
7.5
47
47
47
DR
θ
P-P
-18
JA
)
(Note
8)
with 50% duty cycle, V
(Note
comply
θ
10°C / W
6,
(Note
Package)
JC (Top of
Limits
Note
±0.9
±0.6
−1.5
44.5
44.5
±25
±25
±15
0.5
7.1
7.1
−40°C
8
1,
Note
(100% duty cycle)
0.4V
8)
7)
(10% duty cycle)
with
+1.8V to +2.0V
≤
P-P
V
(Thermal Pad)
2)
2.8°C / W
0V to 2.15V
T
+1.8V to V
CMO
Error/Sample
0V to 2.5V
θ
A
LSB (max)
LSB (max)
LSB (max)
LSB (min)
to 2.0V
mV (max)
mV (max)
Bits (min)
Bits (min)
J-PAD
dB (min)
dB (min)
(Limits)
≤
0V to V
Units
dBFS
National
%FS
±50mV
BG
GHz
Bits
Bits
mV
+85°C
dB
=
0V
P-P
A
A