ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 27

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

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The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in
1.3 THE SERIAL INTERFACE
IMPORTANT NOTE: During the initial write using the serial
interface, all 8 user registers must be written with desired or
default values. In addition, the first write to the DES Enable
register (Dh) must load the default value (0x3FFFh). Once all
registers have been written once, other desired settings, in-
cluding enabling DES can be loaded.
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS) Eight write only registers are acces-
sible through this serial interface.
SCS: This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK: Serial data input is accepted with the rising edge of
this signal. There is no minimum frequency requirement for
SCLK.
SDATA: Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See the Timing Diagram.
Each Register access consists of 32 bits, as shown in
5
0000 0001 (eleven zeros followed by a 1). The loading se-
quence is such that a 0b is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various regis-
ters are indicated in
Refer to the Register Description (Section 1.4) for information
on the data to be written to the registers.
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
does not have to be de-asserted and asserted again between
register addresses. It is possible, although not recommended,
to keep the SCS input permanently enabled (at a logic low)
when using extended control.
Dual Edge Sampling (DES)
of the Timing Diagrams. The fixed header pattern is 0000
LVDS Output Amplitude
SDR or DDR Clocking
Input Offset Adjust
TABLE 3. Extended Control Mode Operation
DDR Clock Phase
Full-Scale Range
Calibration Delay
Table
Feature
3.
Table
(Pin 14 Floating)
4.
Extended Control Mode
Data changes with DCLK
700 mV nominal for both
No adjustment for either
Normal amplitude
edge (0° phase)
DDR Clocking
Default State
Not enabled
(710 mV
Short Delay
channels
channel
P-P
)
Figure
26
IMPORTANT NOTE: The Serial Interface should not be used
when calibrating the ADC. Doing so will impair the perfor-
mance of the device until it is re-calibrated correctly. Pro-
gramming the serial registers will also reduce dynamic
performance of the ADC for the duration of the register access
time.
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A3 loaded after Fixed Header Pattern, A0 loaded last
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TABLE 4. Register Addresses
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Loading Sequence:
4-Bit Address
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Hex
Ah
Bh
Ch
Dh
Eh
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Fh
Register Addressed
DES Coarse Adjust
"Q" Ch Full-Scale
"I" Ch Full-Scale
DES Fine Adjust
Voltage Adjust
Voltage Adjust
Configuration
"Q" Ch Offset
"I" Ch Offset
DES Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved