ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 13

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

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t
t
f
t
t
t
t
t
t
t
OD
WU
SCLK
SSU
SH
CAL
CAL_L
CAL_H
CalDly
CalDly
Symbol
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than V
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two. This limit is not placed upon the power, ground and digital output pins.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 5: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
Note 7: To guarantee accuracy, it is required that V
achieving rated performance requires that the backside exposed pad be well grounded.
Note 8: Typical figures are at T
Level).
Input Clock to Data Output Delay (in
addition to Pipeline Delay)
Pipeline Delay (Latency)
(Note
Over Range Recovery Time
PD low to Rated Accuracy Conversion
(Wake-Up Time)
Serial Clock Frequency
Data to Serial Clock Setup Time
Data to Serial Clock Hold Time
Serial Clock Low Time
Serial Clock High Time
Calibration Cycle Time
CAL Pin Low Time
CAL Pin High Time
Calibration delay determined by pin
127
Calibration delay determined by pin
127
11,
Note
Parameter
A
14)
= 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
A
and V
DR
be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
50% of Input Clock transition to 50% of
Data transition
DI Outputs
DId Outputs
DQ Outputs
DQd Outputs
Differential V
to get accurate conversion
(Note
(Note
(Note
See
See
See Section 1.1.1,
See Section 1.1.1,
Figure 9 (Note
Figure 9 (Note
12)
12)
12)
IN
Conditions
12
step from ±1.2V to 0V
Figure
Figure
11)
11)
Normal Mode
DES Mode
Normal Mode
DES Mode
9,
9,
(Note
(Note
20121404
15)
15)
1.4 x 10
(Note
Typical
500
100
A
3.1
2.5
), the current at that pin should be limited to
1
1
8)
5
(Note
Limits
13.5
14.5
2
2
13
14
13
14
80
80
4
4
25
31
8)
Clock Cycles
Clock Cycles
Clock Cycles
Clock Cycles
Clock Cycles
Clock Cycles
Input Clock
(Limits)
ns (min)
ns (min)
ns (min)
ns (min)
Units
Cycle
(max)
(min)
(min)
(min)
MHz
ns
ns