AD7986BCPZ Analog Devices Inc, AD7986BCPZ Datasheet - Page 20

• Manufacturer Part Number: AD7986BCPZ
• Description: IC ADC 18BIT 2MSPS SAR 20LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD7986BCPZ

• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 18
• Sampling Rate (per Second): 2M
• Number Of Converters: 1
• Power Dissipation (max): 34mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN, CSP Exposed Pad
• Resolution (bits): 18bit
• Sampling Rate: 2MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.375V To 2.625V
• Digital Ic Case Style: CSP
• No. Of Pins: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7986
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7986 is connected
to an SPI-compatible digital host having an interrupt input.
It is only available in normal conversion mode (TURBO = low).
The connection diagram is shown in Figure 27, and the
corresponding timing is given in Figure 28.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. SDO
is maintained in high impedance until the completion of the
conversion irrespective of the state of CNV. Prior to the minimum
conversion time, CNV can be used to select other SPI devices,
such as analog multiplexers, but CNV must be returned low
before the minimum conversion time elapses and then held low
for the maximum possible conversion time to guarantee the
generation of the busy signal indicator.
TURBO = 0
ACQUISITION
SDO
SDI = 1
CNV
SCK
t
CNVH
CONVERSION
t
Figure 28. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
CONV
Figure 27. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
VIO
SDI
AD7986
1
CNV
SCK
t
HSDO
Rev. B | Page 20 of 28
TURBO
D17
2
t
CYC
SDO
ACQUISITION
VIO
D16
t
3
ACQ
47kΩ
t
DSDO
When the conversion is complete, SDO goes from high imped-
ance to low impedance. With a pull-up on the SDO line, this
transition can be used as an interrupt signal to initiate the data
reading controlled by the digital host. The AD7986 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an acceptable
hold time. After the optional 19
to high impedance.
If multiple AD7986 devices are selected at the same time, the
SDO output pin handles this contention without damage or
induced latch-up. Meanwhile, it is recommended to keep this
contention as short as possible to limit extra power dissipation.
t
CONVERT
DATA IN
IRQ
CLK
SCKL
DIGITAL HOST
t
SCKH
17
t
SCK
18
D1
19
D0
(QUIET
TIME)
th
t
DIS
SCK falling edge, SDO returns
t
QUIET