AD7986BCPZ Analog Devices Inc, AD7986BCPZ Datasheet - Page 18

IC ADC 18BIT 2MSPS SAR 20LFCSP

AD7986BCPZ

Manufacturer Part Number
AD7986BCPZ
Description
IC ADC 18BIT 2MSPS SAR 20LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7986BCPZ

Data Interface
MICROWIRE™, QSPI™, Serial, SPI™
Number Of Bits
18
Sampling Rate (per Second)
2M
Number Of Converters
1
Power Dissipation (max)
34mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-VFQFN, CSP Exposed Pad
Resolution (bits)
18bit
Sampling Rate
2MSPS
Input Channel Type
Differential
Supply Voltage Range - Analog
2.375V To 2.625V
Digital Ic Case Style
CSP
No. Of Pins
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7986BCPZ
Manufacturer:
Allen Bradlley
Quantity:
100
Part Number:
AD7986BCPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
AD7986
DATA READING OPTIONS
There are three different data reading options for the AD7986.
There is the option to read during conversion, to split the read
across acquisition and conversion (see Figure 27 and Figure 28),
and in normal mode, to read during acquisition. The desired
SCK frequency largely determines which reading option to
pursue.
Reading During Conversion, Fast Hosts (Turbo or
Normal Mode)
When reading during conversion (n), conversion results are for
the previous (n − 1) conversion. Reading should only occur up
to t
fast SCK.
The required SCK frequency is calculated by
To determine the SCK frequency, follow these examples to read
data from conversion (n − 1).
Turbo mode (2 MSPS):
Normal mode (1.5 MSPS):
The time between t
digital activity should not occur, or sensitive bit decisions may
be corrupt.
Split-Reading, Any Speed Host (Turbo or Normal Mode)
To allow for slower SCK, there is the option of a split read where
data access starts at the current acquisition (n) and spans into the
conversion (n). Conversion results are for the previous (n − 1)
conversion.
Similar to reading during conversion, split-reading should only
occur up to t
restriction is that split-reading take place during the t
(minimum) + t
edge of SCK and CNV rising is an acquisition quiet time, t
DATA
Number_SCK_Edges = 18; t
f
Number_SCK_Edges = 18; t
f
SCK
SCK
f
SCK
and, because this time is limited, the host must use a
= 18/200 ns = 90 MHz
= 18/300 ns = 60 MHz
Number
DATA
DATA
. For the maximum throughput, the only time
DATA
− t
t
_
QUIET
DATA
SCK
and t
time. The time between the falling
_
CONV
Edges
DATA
DATA
is an I/O quiet time where
= 200 ns
= 300 ns
ACQ
QUIET
Rev. B | Page 18 of 28
.
To determine how to split the read for a particular SCK frequency,
follow these examples to read data from conversion (n − 1).
For turbo mode (2 MSPS),
Thirteen bits are read during conversion (n), and five bits are
read during acquisition (n).
For normal mode (1.5 MSPS),
Fifteen bits are read during conversion (n), and three bits are
read during acquisition (n).
For slow throughputs, the time restriction is dictated by the
user’s required throughput, and the host is free to run at any
speed. Similar to the reading during acquisition, for slow hosts,
the data access must take place during the acquisition phase
with additional time into the conversion.
Note that data access spanning conversion requires the CNV to
be driven high to initiate a new conversion, and data access is
not allowed when CNV is high. Thus, the host must perform
two bursts of data access when using this method.
Reading During Acquisition, Any Speed Hosts (Turbo or
Normal Mode)
When reading during acquisition (n), conversion results are
for the previous (n − 1) conversion. Maximum throughput is
achievable in normal mode (1.5 MSPS); however, in turbo
mode, 2 MSPS throughput is not achievable.
For the maximum throughput, the only time restriction is that
the reading takes place during the t
slow throughputs, the time restriction is dictated by throughput
required by the user, and the host is free to run at any speed.
Thus for slow hosts, data access must take place during the
acquisition phase.
f
Number_SCK_Edges = 65 MHz × 200 ns = 13
f
Number_SCK_Edges = 50 MHz × 300 ns = 15
SCK
SCK
= 65 MHz; t
= 50 MHz; t
DATA
DATA
= 200 ns
= 300 ns
ACQ
(minimum) time. For

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