AD7986BCPZ Analog Devices Inc, AD7986BCPZ Datasheet - Page 19

• Manufacturer Part Number: AD7986BCPZ
• Description: IC ADC 18BIT 2MSPS SAR 20LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD7986BCPZ

• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 18
• Sampling Rate (per Second): 2M
• Number Of Converters: 1
• Power Dissipation (max): 34mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN, CSP Exposed Pad
• Resolution (bits): 18bit
• Sampling Rate: 2MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.375V To 2.625V
• Digital Ic Case Style: CSP
• No. Of Pins: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7986 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 25, and the corresponding timing is given in
Figure 26.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. Once
a conversion is initiated, it continues until completion irrespective
of the state of CNV. This can be useful, for instance, to bring
CNV low to select other SPI devices, such as analog multiplexers;
however, CNV must be returned high before the minimum
SDI = 1
ACQUISITION
CNV
SCK
SDO
(n - 1)
t
DIS
END DATA (n – 2)
CONVERSION (n – 1)
t
EN
t
DATA
16
2
>
t
CONV
17
t
CONV
1
Figure 26. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
Figure 25. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
18
0
t
(I/O QUIET
DIS
TIME)
VIO
t
CYC
SDI
t
EN
AD7986
CNV
SCK
17
1
Rev. B | Page 19 of 28
ACQUISITION (n)
16
2
t
SDO
ACQ
BEGIN DATA (n – 1)
15
t
t
conversion time elapses and then held high for the maximum
possible conversion time to avoid the generation of the busy
signal indicator. When the conversion is complete, the AD7986
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate, provided that it has an acceptable hold
time. After the 18
(whichever occurs first), SDO returns to high impedance.
HSDO
DSDO
CONVERT
DATA IN
CLK
DIGITAL HOST
(QUIET
TIME)
t
QUIET
th
t
DIS
SCK falling edge or when CNV goes high
END DATA (n – 1)
t
CONVERSION (n)
CNVH
16
t
2
DATA
t
CONV
17
1
t
SCK
18
0
t
(I/O QUIET
DIS
TIME)
ACQUISITION
AD7986
(n + 1)