LM9822CCWM/NOPB National Semiconductor, LM9822CCWM/NOPB Datasheet
LM9822CCWM/NOPB
Specifications of LM9822CCWM/NOPB
*LM9822CCWM/NOPB
LM9822CCWM
Related parts for LM9822CCWM/NOPB
LM9822CCWM/NOPB Summary of contents
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... Ordering Information Temperature Range 0°C Order Number LM9822CCWM LM9822CCWMX 1 Notes: - Rail transport media, 26 parts per rail, TRI-STATE® registered trademark of National Semiconductor Corporation. ©1999 National Semiconductor Corporation Key Specifications • Output Data Resolution • Pixel Conversion Rate • Analog Supply Voltage • ...
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LM9822 Block Diagram V AGND RED OS CDS from CCD OS G GREEN OS CDS from CCD OS B BLUE OS CDS from CCD VClamp SCLK Serial SDI Interface SDO SEN V A Gain Static Coarse Color ...
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Absolute Maximum Ratings + Positive Supply Voltage ( With Respect GND AGND DGND Voltage On Any Input or Output Pin Input Current at any pin (Note 3) Package Input Current (Note 3) ...
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Electrical Characteristics (Continued) The following specifications apply for AGND=DGND=0V, V for all other limits MIN MAX A Symbol Parameter Internal Reference Characteristics Mid Reference Output Voltage V REFMID Positive Reference ...
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... Note 5: Human body model, 100pF capacitor discharged through a 1.5k Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear Data Book for other methods of soldering surface mount devices. ...
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Electrical Characteristics Note 9: Typicals are =25° 12MHz, and represent most likely parametric norm MCLK Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 11: Full channel integral ...
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Typical Performance Characteristics (Divide by 2, Monochrome Mode, 6 MHz Pixel Rate) Typical 14 Bit DNL 2 1.5 1 LSB 0 4096 8192 Output Code Typical 12 Bit DNL 2 1.5 1 LSB 0.5 0 -0.5 ...
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Pin Descriptions Analog Power V The two pins are the analog supply pins They should be connected to a voltage source of +5V and bypassed to 0.1µF monolithic capacitor in parallel with a 10µF tantalum capacitor. These two ...
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Timing Diagrams MCLK VSMP ADC Clock (internal) N-1 Sample Signal Level Sample Reference Level D7 - N-5 DOE (Register 0, Bit Diagram 1: Divide by 6 Color ...
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Timing Diagrams (Continued MCLK VSMP ADC Clock (internal) N-1 Sample Signal Level Sample Reference Level D7 - N-4 DOE (Register 0, Bit Diagram 4: Divide by 8 Monochrome Mode Sample and Data ...
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Timing Diagrams (Continued MCLK VSMP Sample Signal Sample Reference D3 -D0 Diagram 7: Programmable Reference Sample Timing OS MCLK VSMP CLMP N-1 Sample Signal N Sample Reference CDSREF = 00 Clamp On ...
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Timing Diagrams (Continued) t SCLK SCLK SEN t t SSU SH SDI SDO XX MCLK t t VSU VH VSMP t t CSU CH CLMP DDO Diagram 13: MCLK, VSMP ...
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Table 1: Configuration Register Address Table Address (Binary I/O Mode N/A 0 ...
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Table 2: Configuration Register Parameters Power-Up Default Register Settings are shown in Bold Italics Parameter (Address) B7 I/O Mode 0 ( DOE 0 D7-D0 are clocked out (change) on the falling edge of MCLK - Recommended setting for ...
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Table 2: Configuration Register Parameters Power-Up Default Register Settings are shown in Bold Italics Parameter (Address) Red, Green and Blue Offset DAC Settings (1, 2 & Offset Polarity 1 B4(M Offset Value B3 SB (SIGN ...
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Table 2: Configuration Register Parameters Power-Up Default Register Settings are shown in Bold Italics Parameter (Address (x3) (MSB • • • • • • Typical Gain Values 0 ...
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Applications Information 1.0 Introduction The LM9822 is a high performance scanner Analog Font End (AFE) for image sensor processing systems designed to work with color CCD and CIS image sensors and provides a full 3 channel sampling, gain ...
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Applications Information (Continued) 5.0 Offset DAC The Offset DACs remove the DC offsets generated by the sensor and the LM9822’s analog signal chain (see section 5.1, Internal Offsets). The DAC value for each color (registers 1,2 and 3) should be ...
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Applications Information (Continued) 6.1.1 CDS mode Minimum Clamp Capacitor Calculation: The following equation takes the maximum leakage current into the OS input, the maximum allowable droop, the number of pixels on the sensor, and the pixel conversion rate, f the ...
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Applications Information (Continued) In this example, a 0.01µF capacitor takes 14 lines after power-up to charge to its final value. On subsequent lines, the only error will be the droop across a single line which should be significantly less than ...
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Applications Information (Continued) pling point for particular CCD sensors. Diagram 7 shows how the various settings of CDSREF can be used to delay the Reference Sampling point. Care must be taken to avoid setting CDSREF to an inappropriate value when ...
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