M48T128Y-70PM1 STMicroelectronics, M48T128Y-70PM1 Datasheet - Page 7

• Manufacturer Part Number: M48T128Y-70PM1
• Description: IC TIMEKPR NVRAM 1MBIT 5V 32-DIP
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T128Y-70PM1

• Memory Size: 1M (128K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP (600 mil) Module
• Function: Clock, Calendar, NV Timekeeping RAM, Battery Backup
• Rtc Memory Size: 1 MB
• Supply Voltage (max): 4.5 V to 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2834-5

M48T128Y, M48T128V
2
Note:
Operation modes
Figure 3 on page 6
oscillator. The clock locations contain the year, month, date, day, hour, minute, and second
in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day
months are made automatically. Byte 1FFF8h is the clock control register. This byte controls
user access to the clock information and also stores the clock calibration setting. The seven
clock bytes (1FFFFh - 1FFF8h) are not the actual clock counters, they are memory locations
consisting of BiPORT™ READ/WRITE memory cells within the static RAM array. The
M48T128Y/V includes a clock control circuit which updates the clock bytes with current
information once per second. The information can be accessed by the user in the same
manner as any other location in the static memory array. The M48T128Y/V also has its own
power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an
out of tolerance condition. When V
TIMEKEEPER
unpredictable system operation. As V
(V
operation until valid power is restored.
Table 2.
1. See
X = V
Deselect
Deselect
Deselect
SO
WRITE
READ
READ
Mode
), the control circuitry automatically switches to the battery, maintaining data and clock
IH
Table 11 on page 18
or V
IL
V
Operating modes
SO
; V
®
4.5 to 5.5 V
3.0 to 3.6 V
SO
register data and external SRAM, providing data security in the midst of
to V
≤ V
V
illustrates the static memory array and the quartz controlled clock
= battery backup switchover voltage.
PFD
or
SO
CC
(1)
(min)
for details.
(1)
Doc ID 5746 Rev 6
V
V
V
V
CC
E
X
X
IH
IL
IL
IL
CC
is out of tolerance, the circuit write protects the
falls below the battery backup switchover voltage
V
V
G
X
X
X
X
IH
IL
V
V
V
W
X
X
X
IH
IH
IL
DQ0-DQ7
High Z
High Z
High Z
High Z
D
D
OUT
IN
Battery backup mode
Operation modes
CMOS standby
Standby
Power
Active
Active
Active
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