PCF2123TS/1,118 NXP Semiconductors, PCF2123TS/1,118 Datasheet - Page 37

• Manufacturer Part Number: PCF2123TS/1,118
• Description: IC SPI RTC/CALENDAR 14TSSOP
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF2123TS/1,118

• Package / Case: 14-TSSOP
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Clock/Calendar
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.1 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (3-Wire, SPI)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4534-2; 935286384118; PCF2123TS/1-T

NXP Semiconductors
PCF2123
Product data sheet
9.1 Interface watchdog timer
In
are not connected together. For this configuration, it is important that pin SDI is never left
floating. It must always be driven either HIGH or LOW. If pin SDI is left open, high I
currents may result. Short transition periods in the order of 200 ns will not cause any
problems.
During read/write operations, the time counting circuits are frozen. To prevent a situation
where the accessing device becomes locked and does not clear the interface by setting
pin CE LOW, the PCF2123 has a built in watchdog timer. Should the interface be active
for more than 1 s from the time a valid subaddress is transmitted, then the PCF2123 will
automatically clear the interface and allow the time counting circuits to continue counting.
CE must return LOW once more before a new data transfer can be executed.
The watchdog is implemented to prevent the excessive loss of time due to interface
access failure e.g. if main power is removed from a battery backed-up system during an
interface access.
Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The
watchdog will trigger between 1 s and 2 s after receiving a valid subaddress.
Fig 26. Interface watchdog timer
Figure
a. Correct data transfer: read or write
b. Incorrect data transfer: read or write
25, the Months and Years registers are read. In this example, pins SDI and SDO
WD timer
WD timer
counters
counters
data
time
data
time
CE
CE
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 April 2011
valid sub-address
valid sub-address
running
running
data
data
time counters frozen
WD timer running
t
w(CE)
data
data
time counters frozen
WD timer running
1 s < t
< 1 s
data
data
w(CE)
< 2 s
data transfer fail
SPI Real time clock/calendar
running
WD trips
PCF2123
© NXP B.V. 2011. All rights reserved.
running
001aai563
001aai564
DD
37 of 63