SI4133T-BM Silicon Laboratories Inc, SI4133T-BM Datasheet - Page 36

IC RF SYNTHESIZER DUAL 28MLP

SI4133T-BM

Manufacturer Part Number
SI4133T-BM
Description
IC RF SYNTHESIZER DUAL 28MLP
Manufacturer
Silicon Laboratories Inc
Type
Frequency Synthesizerr
Datasheets

Specifications of SI4133T-BM

Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
No/No
Frequency - Max
1.8GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Frequency-max
1.8GHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Aero
Register 31h. Main Configuration (Si4133T)
36
Name
Bit
17:15
14:11
10:5
Bit
2:1
4
3
0
D17 D16 D15 D14 D13 D12 D11 D10 D9
0
0
SDOSEL[3:0]
Reserved
Reserved
Reserved
Reserved
0
Name
RFUP
DIV2
SDOSEL[3:0]
SDO Output Control Register.
The mux_output table is as follows:
0000 Connected to the Output Shift Register (default).
0001 Force the Output to Low.
0010 Reference Clock.
0011 Lock Detect (LDETB) Signal from Phase Detectors.
1111 High Impedance.
Notes:
Program to zero.
RF PLL Update Rate (RF1 VCO only).
0 = 200 kHz update rate (Receive GSM modes).
1 = 100 kHz update rate (Receive DCS and PCS modes).
Note: This bit is set to 1 when register 20h D[17:16] = 01
Input Clock Frequency.
0 = No divider. XIN = 13 MHz.
1 = Divide XIN by 2. XIN = 26 MHz.
Program to zero.
Program to one.
Program to zero.
1. SDO is high-impedance when PDN = 0.
2. SDO is Serial Data Output when in register read mode.
PCS 1900 receive modes) and is set to 0 when D[17:16] = 00
(GSM 850 or GSM 900 modes).
0
Rev. 1.4
0
D8
0
D7
0
Function
D6
0
D5
0
RFUP
D4
DIV2
D3
b
or 10
D2
b
0
(DCS 1800 or
b
or 11
D1
0
b
D0
1

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