SI4133T-BM Silicon Laboratories Inc, SI4133T-BM Datasheet - Page 24

• Manufacturer Part Number: SI4133T-BM
• Description: IC RF SYNTHESIZER DUAL 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4133T-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Aero
4.5. Serial Interface
A three-wire serial interface is provided to allow an
external system controller to write the control registers
for dividers, receive path gain, powerdown settings, and
other controls. The serial control word is 24 bits in
length, comprised of an 18-bit data field and a 6-bit
address field as shown in Figure 17. A single logical
register space is shared among the three chips, which is
summarized in Table 10 on page 25.
The serial interface pins are intended to be connected in
parallel to both the Si4201 and the Si4133T. Serial
control is relayed from the Si4201 to the Si4200 over
the signal interface (IOP/ION and CKP/CKN pins). All
registers must be written when the PDN pin is asserted
(low), except for register 22h. All serial interface pins
should be held at a constant level during receive and
transmit bursts to minimize spurious emissions. This
includes stopping the SCLK clock. A timing diagram for
the serial interface is shown in Figure 3 on page 7.
When the serial interface is enabled (i.e., when SEN is
low), data and address bits on the SDI pin are clocked
into an internal shift register on the rising edge of SCLK.
Data in the shift register is then transferred on the rising
edge of SEN into the internal data register addressed in
the address field. The internal shift register ignores any
leading bits before the 24 required bits. The serial
interface is disabled when SEN is high.
Optionally, registers can be read as illustrated in
Figure 4 on page 7. The serial output data appears on
the SDO pin after writing the revision register with the
address to be read. SDO is enabled when PDN = 0 on
the Si4201 and when PDN = 1 on the Si4133T, allowing
the SDO pin to be shared. Writing to any of the registers
causes the function of SDO to revert to its previously
programmed function.
24
17
D
16
D
15
D
Figure 17. Serial Interface Format
14
D
13
D
12
D
11
D
10
D
Data Field
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
Address
A
3
Field
A
2
clocked in
A
1
Last bit
A
0
Rev. 1.4
4.6. XOUT Buffer
The Si4201 contains a reference clock buffer to drive
the baseband input. The clock signal from the VC-
TCXO is capacitively coupled to the XIN pin on the
Si4201. The clock signal is not divided with the XSEL
control.
The XOUT buffer is a CMOS driver stage with
approximately 250 Ω of series resistance. This buffer is
enabled when the XEN hardware control (pin 13 on the
Si4201) is set high, independent of the PDN control pin.
To achieve complete powerdown during sleep, the XEN
pin must be set low, the XBUF bit in Register 12 must
be set to zero, and the XPD1 bit in Register 11 must be
set to one. During normal operation, these bits should
set to their default values.