MPC9772AE Freescale Semiconductor, MPC9772AE Datasheet - Page 7
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MPC9772AE
Manufacturer Part Number
MPC9772AE
Description
IC PLL CLK GENERATOR 1:12 52LQFP
Manufacturer
Freescale Semiconductor
Type
Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr
Datasheet
1.MPC9772FA.pdf
(16 pages)
Specifications of MPC9772AE
Pll
Yes with Bypass
Input
LVCMOS
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
3:12
Differential - Input:output
No/No
Frequency - Max
240MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
52-LQFP
Frequency-max
240MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC9772AE
Manufacturer:
IDT
Quantity:
465
Company:
Part Number:
MPC9772AE
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
MPC9772AER2
Manufacturer:
IDT
Quantity:
1 539
Company:
Part Number:
MPC9772AER2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Table 10. AC Characteristics (V
1. AC characteristics apply for parallel output termination of 50Ω to V
2. In bypass mode, the MPC9772 divides the input reference clock.
3. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f
4. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio:
5. Calculation of reference duty cycle limits: DC
6. The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t
7. Static phase offset depends on the reference frequency. t
8. Excluding QSYNC output. See application section for part-to-part skew calculation.
9. Output duty cycle is DC = (0.5 ± 200 ps ⋅ f
10. Cycle jitter is valid for all outputs in the same divider configuration. See application section for more details.
11. Period jitter is valid for all outputs in the same divider configuration. See application section for more details.
12. I/O jitter is valid for a VCO frequency of 400 MHz. See application section for I/O jitter vs. VCO frequency.
13. –3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
t
BW
t
JIT(∅)
LOCK
Symbol
f
guaranteed if t
XTAL(min, max)
I/O Phase Jitter RMS (1 σ)
PLL closed loop bandwidth
Maximum PLL Lock Time
= f
R
, t
VCO(min, max)
F
are within the specified range.
Characteristics
÷ (M ⋅ VCO_SEL) and 10 MHz ≤ f
CC
Freescale Semiconductor, Inc.
12
13
= 3.3V ± 5%, T
For More Information On This Product,
OUT
REF,MIN
)
⋅
100%. E.g. the DC range at f
Go to: www.freescale.com
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
÷4 feedback
÷6 feedback
÷8 feedback
÷4 feedback
÷6 feedback
÷8 feedback
= t
A
PW,MIN
= –40° to +85°C)
(∅)
[s] = t
⋅ f
XTAL
REF
(∅)
TT
7
[°] ÷ (f
.
≤ 25 MHz.
⋅ 100% and DC
Min
REF
1 2
OUT
⋅ 360°).
(Continued)
= 100 MHz is 48%<DC<52%. T = output period.
1.20 –
0.70 –
0.50 –
0.45 –
0.30 –
0.25 –
0.20 –
0.17 –
0.12 –
0.11 –
Typ
3.50
2.50
1.80
1.20
1.00
0.70
0.55
0.40
0.30
0.28
REF,MAX
= 100% – DC
to +70°C
T
A
= 0°C
Max
11
86
13
88
16
19
21
22
27
30
10
T
to +85°C
(∅)
A
REF, MIN
REF
= –40°C
, t
PW,MIN
= f
VCO
.
, DC and f
÷ (M
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ms
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
⋅
VCO_SEL).
(VCO=400 MHz)
MAX
MPC9772
Condition
MOTOROLA
can only be