LMX2370TM National Semiconductor, LMX2370TM Datasheet - Page 22

• Manufacturer Part Number: LMX2370TM
• Description: IC FREQ SYNTH DL 2.5GHZ 20TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2370TM

• Pll: Yes with Bypass
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 2.5GHz, 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 2.5GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LMX2370TM

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Application Information
other terms in the gain and phase Equations (5), (6) will have
to compensate by the corresponding “1/w” or “1/w
Examination of Equations (3), (4), (6) indicates the damping
resistor variable R2 could be chosen to compensate the “w”
terms for the phase margin. This implies that another resistor
of equal value to R2 will need to be switched in parallel with
R2 during the initial lock period. We must also ensure that
FASTLOCK CIRCUIT IMPLEMENTATION
A diagram of the Fastlock scheme as implemented in Na-
tional Semiconductors LMX233xA PLL is shown in Figure 5.
When a new frequency is loaded, and the RF Icp
high the charge pump circuit receives an input to deliver 4
times the normal current per unit phase error while an open
drain NMOS on chip device switches in a second R2 resistor
element to ground. The user calculates the loop filter com-
ponent values for the normal steady state considerations.
The device configuration ensures that as long as a second
FIGURE 4. Open Loop Response Bode Plot
(Continued)
FIGURE 5. Fastlock PLL Architecture
o
2
bit is set
” factor.
22
the magnitude of the open loop gain, H(s)G(s) is equal to
zero at wp’ = 2wp. K
terms can be changed by a factor of 4, to counteract the w
term present in the denominator of Equations (3), (4). The Kφ
term was chosen to complete the transformation because it
can readily be switch between 1X and 4X values. This is
accomplished by increasing the charge pump output current
from 1 mA in the standard mode to 4 mA in Fastlock.
identical damping resistor is wired in appropriately, the loop
will lock faster without any additional stability considerations
to account for. Once locked on the correct frequency, the
user can return the PLL to standard low noise operation by
sending a MICROWIRE instruction with the RF Icp
low. This transition does not affect the charge on the loop
filter capacitors and is enacted synchronous with the charge
pump output. This creates a nearly seamless change be-
tween Fastlock and standard mode.
VCO
, Kφ, N, or the net product of these
10102643
10102644
o
bit set
2