LMX2370TM National Semiconductor, LMX2370TM Datasheet - Page 21

• Manufacturer Part Number: LMX2370TM
• Description: IC FREQ SYNTH DL 2.5GHZ 20TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2370TM

• Pll: Yes with Bypass
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 2.5GHz, 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 2.5GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LMX2370TM

Application Information
A block diagram of the basic phase locked loop is shown in
Figure 1.
LOOP GAIN EQUATIONS
A linear control system model of the phase feedback for a
PLL in the locked state is shown in Figure 2. The open loop
gain is the product of the phase comparator gain (Kφ), the
VCO gain (K
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in Figure 3, while
the complex impedance of the filter is given in Equation (2).
The time constants which determine the pole and zero fre-
quencies of the filter transfer function can be defined as
VCO
FIGURE 3. Passive Loop Filter
FIGURE 2. PLL Linear Model
/s), and the loop filter gain Z(s) divided by
FIGURE 1. Basic Charge Pump Phase Locked Loop
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(1)
(2)
21
and
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, ω, the filter time constants T1 and T2,
and the design constants K
From Equation (3) we can see that the phase term will be
dependent on the single pole and zero such that the phase
margin is determined in Equation (6).
A plot of the magnitude and phase of G(s)H(s) for a stable
loop, is shown in Figure 4 with a solid trace. The parameter
φ
the gain drops below zero (the cutoff frequency wp of the
loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop band-
width, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison
frequency also diminishes, the spurs would have increased
by approximately 6 dB. In the proposed Fastlock scheme,
the higher spur levels and wider loop filter conditions would
exist only during the initial lock-on phase — just long enough
to reap the benefits of locking faster. The objective would be
to open up the loop bandwidth but not introduce any addi-
tional complications or compromises related to our original
design criteria. We would ideally like to momentarily shift the
curve of Figure 4 over to a different cutoff frequency, illus-
trated by the dotted line, without affecting the relative open
loop gain and phase relationships. To maintain the same
gain/phase relationship at twice the original cutoff frequency,
p
shows the amount of phase margin that exists at the point
φ(ω) = tan
−1
(ω • T2) − tan
T2 = R2 • C2
φ
, K
VCO
−1
, and N.
(ω • T1) + 180˚
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(3)
(4)
(5)
(6)