LMX2352TMX/NOPB National Semiconductor, LMX2352TMX/NOPB Datasheet - Page 13

• Manufacturer Part Number: LMX2352TMX/NOPB
• Description: IC FREQ SYNTHESIZER DUAL 24TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2352TMX/NOPB

• Pll: Yes with Bypass
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 1.2GHz, 550MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2352TMX; LMX2352TMXTR

Programming Description
3.1.3 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Notes: Divide ratio: 3 to 32,767 (Divide ratios less than 3 are prohibited).
RF_R_CNTR/IF_R_CNTR These bits select the divide ratio of the programmable reference dividers.
3.1.4 IF_CP_WORD
CP_GAIN_8 is used to toggle the IF charge pump current magnitude between 1x mode (100 uA typ) and 8x mode (800uA typ).
IF_PD_POL is set to one when IF VCO characteristics are positive. When IF VCO frequency decreases with increasing control
voltage IF_PD_POL should set to zero.
3.1.5 FoLD* Programming Truth Table
*FoLD - Fout/Lock Detect PROGRAMMING BITS
3.2 RF_R Register
If the Control Bits (CTL [1:0]) are 1 0, data is transferred from the 24-bit shift register into the RF_R register latch which sets the
RF PLL 15-bit R counter divide ratio. The divide ratio is programmed using the RF_R_CNTR word as shown in table 3.1.3. The
divide ratio must be
detailed in 3.2.2.
Divide Ratio
MSB
DLL_MODE
23
32,767
BIT
CP_GAIN_8
IF_PD_POL
IF_CP_WORD
CP_GAIN_8
3
4
-
14
0
0
1
-
FoLD
0 0 0
1 0 0
0 1 0
1 1 0
0 0 1
1 0 1
0 1 1
1 1 1
3. The bits used to control the voltage doubler (V2_EN) and RF Charge Pump (RF_CP_WORD) are
V2_EN
13
22
0
0
1
LOCATION
IF_R [18]
IF_R [17]
-
(IF_R[17]-[18])
(IF_R [17] - [18] )
IF_PD_POL
12
0
0
1
-
RF_CP_WORD [4:0]
21
(Continued)
11
0
0
1
-
(IF_R[19]-[21])
IF_R_CNTR/RF_R_CNTR
FUNCTION
IF Charge Pump Current Gain
IF Phase Detector Polarity
10
0
0
1
-
9
0
0
1
-
13
17
8
0
0
1
-
Fo/LD OUTPUT STATE
IF and RF Analog Lock Detect (Open Drain)
IF Digital Lock Detect
RF Digital Lock Detect
IF and RF Digital Lock Detect
IF R counter
IF N counter
RF R counter
RF N counter
7
0
0
1
RF_R_CNTR [14:0]
16
-
6
0
0
1
-
5
0
0
1
-
(IF_R[2]-[16])
0
1X
Negative
4
0
0
1
-
2
3
0
0
1
-
2
0
1
1
-
1
1
1
8X
Positive
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1
1
0
1
-
LSB
0
0
0
1
0
1
-