IDT5V9885PFGI IDT, Integrated Device Technology Inc, IDT5V9885PFGI Datasheet - Page 13

• Manufacturer Part Number: IDT5V9885PFGI
• Description: IC CLK GEN 3.3V EEPROM 32-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5V9885PFGI

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 500MHz
• Number Of Elements: 3
• Supply Current: 120mA
• Pll Input Freq (min): 1MHz
• Pll Input Freq (max): 400MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Output Frequency Range: 0.0049 to 500MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5V9885PFGI; 800-1992; IDT5V9885PFGI

parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain loop stability.
the ωp / ωc ratio should be at least 4. Given Fc and M, an optimal loop filter setting needs to be solved for that will meet both the PLL loop bandwidth and maintain
loop stability.
possible values within the loop filter settings are 12.55pF (CP[3:0]=1111), 196.4pF (CZ[3:0]=0111), and 15.3KΩ (RZ[3:0]=1111), respectively. This loop filter
setting will yield a loop bandwidth of about 102KHz. The phase margin must be checked for loop stability.
IDT5V9885
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
To determine if the loop is stable, the phase margin (ωm) would need to be calculated as follows.
Phase Margin:
ωz = 1 / (Rz * Cz)
ωp = Cz + Cp
φm = (360 / 2π ) * [tan
To ensure stability in the loop, the phase margin is recommended to be > 60° but too high will result in the lock time being excessively long. Certain loop filter
Example
Fc = 150KHz is the desired loop bandwidth. The total M value is 850. The ratio of ωp/ωc should be at least 4. A rule of thumb that will help to aid the way,
The charge pump gain should be relatively small as possible to achieve a low loop bandwidth.
Ip = 40uA .
Kφ * K
Loop Bandwidths
ωc = 2π * Fc = 9.42x10
ωuz = ωp / ωc = 4
ωc
ωp = Cz + Cp = ωz (1 + Cz / Cp)
Solving for Cz, Cp, and Rz
Knowing ωc = Rz * Kφ * K
Cz >>> Cp, therefore, we can easily derive Cp to be
Cp = Kφ * K
Similarly for Cz and Rz
Cz = Kφ * K
Rz =
Based on the loop filter parameter equations from above, since there are no possible values of 12.60pF for Cp, 189pF for Cz, and 22.48KΩ for Rz, the next
φm = (360 / 2π ) * [tan
Although slightly below 60°, the phase margin would be acceptable with a fairly stable loop.
2
= ωp * ωz
Rz * Cz * Cp
Rz * Cz * Cp
M * ωc
Kφ * K
VCO
M * ωc * ωuz
= 950MHz/V * 40uA = 38000A/Vs
VCO
2
VCO
VCO
* ωuz
* (ωuz
M * (Cz + Cp)
M * ωc
* (ωuz
2
-1
-1
= 12.60pF
(ωc/ ωz) - tan
5
2
(6.41x10
2
2
s
- 1)
VCO
* ωuz
- 1) = Cp * (ωuz
-1
(Eq. 23)
(Eq. 24)
(Eq. 26)
(Eq. 27)
= 22.48KΩ
* Cz and substituting in the equations from above,
5
s
-1
-1
/ 3.33x10
(ωc/ ωp)]
2
- 1) = 189pF
5
s
-1
) - tan
-1
(Eq. 25)
(6.41x10
5
s
-1
13
/ 5.54x10
6
s
-1
)] = 56°
INDUSTRIAL TEMPERATURE RANGE