IDT5V9885NLGI8 IDT, Integrated Device Technology Inc, IDT5V9885NLGI8 Datasheet - Page 14

• Manufacturer Part Number: IDT5V9885NLGI8
• Description: IC CLK GEN 3.3V EEPROM 28-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5V9885NLGI8

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN, 28-VFQFPN
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5V9885NLGI8

The post-divider should never be disabled in any of the two P configurations unless the output bank will never be used during normal operation. The PLL's
loop filter settings also has four different configurations to store and select from. This will be explained in the MODE1 and MODE2 sections. The use of the GINx
pins in MFC mode control the selection of these configurations.
GIN1 and GIN2 pins control the selection of up to eight different D0, M0, P, RZ0, CZ0, PZ0, and IP0 stored configurations. GIN3 becomes PLL SUSPEND pin,
GIN4 is not available to users, and GIN5 becomes CLK_SEL pin. The output GOUT0 will become an indicator for loss of PLL lock (LOSS_LOCK).
to provide eight different stored configurations. PLL1 and PLL2 will still be fully operational but the default configuration will be Config0. The output banks will
each have two P configurations that can be associated with each of the PLL configurations. Each of the two P configurations has its own set of PM bits (See the
PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail on the PM bits). Use the ODIV bit to choose which post-divider configuration
to associate with a specific PLL configuration. For example, if ODIV0_CONFIG0=1, then when Config0 is selected Qx[9:0]_CONFIG1 is selected as the post-
divider value to be used. Or if ODIV2_CONFIG3 = 0, then when CONFIG7 is selected, Qx[9:0]_CONFIG0 is selected. Note that there is an ODIVx bit for each
of the PLL configurations. In this way, the post-divider values can change with the configuration.
CONFIGURING THE MULTI-PURPOSE I/Os
(GIN0, GIN1, GIN2, GIN3, GIN4, GIN5) have different uses depending on the mode of operation. The four available modes of operation are:
NOTE:
1.
IDT5V9885
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Each PLL's programming registers can store up to four different Dx and Mx configurations in combination with two different P configurations in MFC modes.
MODE1 - Manual Frequency Control (MFC) Mode for PLL0 Only
In this mode, only the configuration of PLL0 can be changed during operation.. PLL1 and PLL2 have only one fixed configuration in this mode. The GIN0,
GOUT1 pin will become an indicator for loss of the selected clock (LOSS_CLKIN).
PLL0 itself only has four different configurations to choose from but in this mode, it borrows two configurations (Config2 and Config3) from both PLL1 and PLL2,
To enter this mode, users must set MFC bit to "1", and I
The 5V9885 can operate in four distinct modes. These modes are controlled by the MFC bit (0x04) and the I
1)
2)
3)
4)
Along with the GINx pins are also GOUTx output pins that can take up a different function depending on the mode of operation. See table below for description.
LOSS_LOCK and LOSS_CLKIN cannot be used as reliable inputs to other devices.
Multi-Purpose Pins
GIN2 Pin
Manual Frequency Control (MFC) Mode for PLL0 Only
Manual Frequency Control (MFC) Mode for all three PLLs
I
JTAG Programming Mode
2
0
0
0
0
1
1
1
1
C Programming Mode
GOUT0
GOUT1
GIN0
GIN1
GIN2
GIN3
GIN4
GIN1 Pin
Other Signal Functions
TDO / LOSS_LOCK
0
0
1
1
0
0
1
1
LOSS_CLKIN
SCLK / TCK
SDAT / TDI
CLK_SEL
TRST
TMS
GIN0 Pin
2
C/JTAG pin must be left floating.
0
1
0
1
0
1
0
1
I
I
JTAG control signal to the TAP controller state machine
JTAG active LOW input to asynchronously reset the BST
Reference clock select between XTALIN/REFIN and CLKIN
Detects loss of the selected clock source
JTAG serial data output / Detects loss of PLL lock
2
2
C serial data input / JTAG serial data input
C clock input / JTAG clock input
14
Configuration 0: D0_CONFIG0, M0_CONFIG0, and ODIV0_CONFIG0
Configuration 1: D0_CONFIG1, M0_CONFIG1, and ODIV0_CONFIG1
Configuration 2: D0_CONFIG2, M0_CONFIG2, and ODIV0_CONFIG2
Configuration 3: D0_CONFIG3, M0_CONFIG3, and ODIV0_CONFIG3
Configuration 4: D1_CONFIG2, M1_CONFIG2, and ODIV1_CONFIG2
Configuration 5: D1_CONFIG3, M1_CONFIG3, and ODIV1_CONFIG3
Configuration 6: D2_CONFIG2, M2_CONFIG2, and ODIV2_CONFIG2
Configuration 7: D2_CONFIG3, M2_CONFIG3, and ODIV2_CONFIG3
PLL0 Configuration Selection (Mode 1)
Signal Description
(1)
2
INDUSTRIAL TEMPERATURE RANGE
C/JTAG pin. The general purpose I/O pins
(1)