LMX2470SLEX National Semiconductor, LMX2470SLEX Datasheet - Page 26

• Manufacturer Part Number: LMX2470SLEX
• Description: IC PLL DELTA-SIGMA 24LAMUCSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2470SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 2.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 2.6GHz
• For Use With: LMX2470EVAL - EVALUATION BOARD FOR LMX2470
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMX2470SLEX; *LMX2470SLEX/NOPB; LMX2470SLEXCT

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REGISTER
Programming Description
2.1 R0 REGISTER
Note that this register has only one control bit. The reason for this is that it enables the N counter value to be changed with a
single write statement to the PLL.
2.1.1 RF_FN[11:0] -- Fractional Numerator for RF PLL
Refer to section 2.8.1 for a more detailed description of this control word.
2.1.2 RF_N[10:0] -- RF N Counter Value
The RF N counter contains a 16/17/20/21 prescaler. Because there is only one selection of prescaler, the value that is
programmed is simply the N counter value converted into binary form. However, because this counter does have a prescaler,
there are limitations on the divider values.
R0
2041-2044
2045-2046
>
RF_N
2040
≤65
2046
66
67
68
69
...
23
22
0
0
1
.
21
20
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
0
0
1
.
19
RF_N[10:0]
18
0
0
1
.
Possible with a second or third order delta-sigma engine.
Possible with a second or third order delta-sigma engine.
17
Possible only with a second order delta-sigma engine.
Possible only with a second order delta-sigma engine
(Continued)
N values less than or equal to 65 are prohibited.
RF_C
16
0
0
1
.
N values above 2046 are prohibited.
15
14
1
1
1
.
26
13
RF_N[10:0]
0
0
1
.
12
11
0
0
1
.
10
9
0
0
1
8
.
RF_B
FN[11:0]
7
6
1
1
0
.
5
4
C3
3
0
0
0
.
RF_A
C2
2
C1
1
0
1
0
.
C0
0
0