LMX2470SLEX National Semiconductor, LMX2470SLEX Datasheet - Page 23

• Manufacturer Part Number: LMX2470SLEX
• Description: IC PLL DELTA-SIGMA 24LAMUCSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2470SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 2.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 2.6GHz
• For Use With: LMX2470EVAL - EVALUATION BOARD FOR LMX2470
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMX2470SLEX; *LMX2470SLEX/NOPB; LMX2470SLEXCT

Functional Description
1.6.5 Capacitor Dielectric Considerations for Lock
Time
The LMX2470 has a high fractional modulus and high
charge pump gain for the lowest possible phase noise. One
consideration is that the reduced N value and higher charge
pump may cause the capacitors in the loop filter to become
larger in value. For larger capacitor values, it is common to
have a trade-off between capacitor dielectric quality and
physical size. Using film capacitors or NP0/CG0 capacitors
yields the best possible lock times, where as using X7R or
Z5R capacitors can increase lock time by 0 – 500%. How-
ever, it is a general tendency that designs that use a higher
compare frequency tend to be less sensitive to the effects of
capacitor dielectrics. Although the use of lesser quality di-
electric capacitors may be unavoidable in many circum-
stances, allowing a larger footprint for the loop filter capaci-
tors, using a lower charge pump current, and reducing the
fractional modulus are all ways to reduce capacitor values.
Capacitor dielectrics have very little impact on phase noise
and spurs.
1.7 FRACTIONAL SPUR AND PHASE NOISE
CONTROLS FOR THE LMX2470
The LMX2470 has several bits that have a large impact on
fractional spurs. These bits also have a lesser effect on
phase noise. The control words in question are CPUD[2:0],
FM[1:0], and DITH[1:0]. It is difficult to predict which settings
will be optimal for a particular application without testing
them, but the general recipe for using these bits can be
seen.
A good algorithm is to start with a 3rd order fractional modu-
lator (FM=3) and dithering disabled. Then depending on
whether phase noise, fractional spurs, or sub-fractional
spurs are most important, optimize the settings. Integer
spurs and fractional spurs are nothing new, but sub-
fractional spurs are something unique to delta-sigma PLLs.
These are spurs that occur at a fraction of the frequency of
where a fractional spur would appear.
First adjust the delta-sigma modulator order. Often increas-
ing from a 2nd to a 3rd order modulator provides a large
benefit in spur levels. Increasing from a 3rd to a 4th order
modulator usually provides some benefit, but it is usually on
the order of a few dB. The modulator order by far has the
greatest impact on the main fractional spurs. If the loop
bandwidth is very wide, or the loop filter order is not high
enough, higher order modulators will introduce a lot of sub-
(Continued)
23
fractional spurs. The second order modulator usually does
not have these sub-fractional spurs. The third order modu-
lator will introduce them at
would expect to see a traditional fractional spur, thus the
name "sub-fractional spur". The fourth order modulator will
introduce these spurs at
fractional spur would be. If the benefit of using a higher order
modulator seems significant enough, it may make sense to
try to compensate for them using the other two test bits, or
designing a higher order loop filter. Be aware that the impact
of the modulator order on the spurs may not be consistent
across tuning voltage. When the charge pump mismatch is
not so bad, the lower order modulators may seem to outper-
form the higher order modulators, but when the worst case
fractional spurs are considered over the whole range, often
the higher order modulator performs better.
Second, adjust with the CPUD[2:0] bits. Setting this bit to
maximum tends to reduce the sub-fractional spurs the most,
however, it may degrade phase noise by up to 1 dB.
Third, experiment with the dithering. When dithering is en-
abled, it may increase phase noise by up to 2 dB. However,
enabling dithering may also reduce the sub-fractional spurs.
Also, sometimes both the fractional spurs and the sub-
fractional spurs can be unpredictable with dithering disabled.
This is because the delta-sigma sequence is periodic, but
the starting point changes. Dithering takes these problems
away. When the fractional numerator is 0, enabling dithering
typically hurts spur performance, because it is trying to cor-
rect for spur that are not there.
Fourth, consider experimenting with the loop filter order and
comparison frequency. In general, higher order loop filters
are always better, but they require more components. Often,
the best spur performance is at higher comparison frequen-
cies as well. The reason why this is the last step is not
because it has the least impact, but because it takes more
labor to do this than to change the FM[1:0], CPUD[2:0], and
DITH[1:0] bits.
Although general trends do exist, the optimal settings for test
bits may depend on the comparison frequency and loop
filter. Also the output frequency in important. In particular, the
charge pump tuning voltage is relevant. The recommended
way to do this is to test the spur levels at the low, middle, and
high range of the VCO, and use the worst case over these
three frequencies as a metric for performance. Also, it is
important to be aware that all the rules stated above have
counterexamples and exceptions. However, more often than
not, these rules apply.
1
⁄
2
1
⁄
2
and
of the frequency where one
1
⁄
4
of where a traditional
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