LMX2470SLEX National Semiconductor, LMX2470SLEX Datasheet - Page 19
![IC PLL DELTA-SIGMA 24LAMUCSP](/photos/6/56/65643/14-24-laminate_csp_sml.jpg)
LMX2470SLEX
Manufacturer Part Number
LMX2470SLEX
Description
IC PLL DELTA-SIGMA 24LAMUCSP
Manufacturer
National Semiconductor
Type
PLL Frequency Synthesizer, Delta Sigmar
Datasheet
1.LMX2470SLEXNOPB.pdf
(36 pages)
Specifications of LMX2470SLEX
Pll
Yes with Bypass
Input
CMOS
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
3:3
Differential - Input:output
Yes/No
Frequency - Max
2.6GHz
Divider/multiplier
Yes/Yes
Voltage - Supply
2.25 V ~ 2.75 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-Laminate UTCSP
Frequency-max
2.6GHz
For Use With
LMX2470EVAL - EVALUATION BOARD FOR LMX2470
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*LMX2470SLEX
*LMX2470SLEX/NOPB
LMX2470SLEXCT
*LMX2470SLEX/NOPB
LMX2470SLEXCT
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Functional Description
1.4 DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the differ-
ence between the phase of the inputs of the phase detector
to a RC generated delay of 10 nS. To enter the locked state
(Lock = HIGH) the phase error must be less than the 10nS
RC delay for 5 consecutive reference cycles. Once in lock
(Lock = HIGH), the RC delay is changed to approximately
20nS. To exit the locked state (Lock = LOW), the phase error
must become greater than the 20nS RC delay. When the
PLL is in the power down mode, Lock is forced LOW. For the
(Continued)
19
RF PLL, the digital lock detect circuitry does not function
reliably for comparison frequencies above 20 MHz.
The IF PLL digital lock detect circuitry works in a very similar
way as the RF PLL digitial lock circuitry, except that it uses a
delay of less than 15 nS for 5 reference cycles to determine
a locked condition and a delay of greater than 30 nS to
determine the IF PLL is unlocked. Note that if the MUX[3:0]
word is set such as to view lock detect for both PLLs, an
unlocked (LOW) condition is shown whenever either one of
the PLLs is determined to be out of lock. A flow chart of the
IF digital lock detect circuitry is shown below.
20059304
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