IDT82V3280PFG8 IDT, Integrated Device Technology Inc, IDT82V3280PFG8 Datasheet - Page 7
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IDT82V3280PFG8
Manufacturer Part Number
IDT82V3280PFG8
Description
IC PLL WAN SE STRATUM 2 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of IDT82V3280PFG8
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
622.08MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3280PFG8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3280PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT82V3280
WAN PLL
Table 49: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 154
Table 50: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 154
Table 51: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 154
Table 52: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 156
Table 53: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 157
Table 54: Output Clock Jitter Generation .................................................................................................................................................................. 158
Table 55: Output Clock Phase Noise ......................................................................................................................................................................... 159
Table 56: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 159
Table 57: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 159
Table 58: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 159
Table 59: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 159
Table 60: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 160
Table 61: T4 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 160
Table 62: Input/Output Clock Timing 3 ...................................................................................................................................................................... 162
Table 63: Output Clock Timing .................................................................................................................................................................................. 163
List of Tables
7
December 9, 2008