STW81102ATR STMicroelectronics, STW81102ATR Datasheet - Page 24

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STW81102ATR

Manufacturer Part Number
STW81102ATR
Description
IC SYNTHESIZER MULTI RF 28VFQFPN
Manufacturer
STMicroelectronics
Type
Frequency Synthesizerr
Datasheet

Specifications of STW81102ATR

Pll
Yes
Input
Clock, Crystal
Output
Clock, Crystal
Number Of Circuits
1
Ratio - Input:output
3:2
Differential - Input:output
No/No
Frequency - Max
4.65GHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-VFQFN, 28-VFQFPN
Frequency-max
4.65GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Circuit description
5.8.3
24/53
The SERCAL bit should be set to 1 at each division ratio change. VCO calibration procedure
takes approximately 7 periods of the PFD frequency.
The maximum allowed F
higher F
1.
2.
VCO calibration auto-restart feature
The VCO calibration auto-restart feature, once activated, allows to restart the calibration
procedure when the Lock Detector reports that the PLL has moved to an unlock condition
(trigger on ‘1’ to ‘0’ transition of Lock Detector signal).
This situation could happen if the device experiences a significant temperature variation.
Once programmed at the initial temperature T
(-40 °C to +85 °C), the synthesizer is able to maintain the lock status only if the temperature
drift (in either direction) is within the limit specified by the ΔT
final temperature T
Each VCO featured by STW81102 has its specific ΔT
is typically lower than the maximum allowable drift (ΔT
vice versa).
By enabling the VCO Calibration Auto-Restart feature (through the CAL_AUTOSTART_EN
bit), the part will be able to select again the proper VCO frequency sub-range if the
temperature drift exceeds the ΔT
VCO voltage amplitude control
The voltage swing of the VCOs can be adjusted over four levels by means of two dedicated
programming bits (PLL_A1 and PLL_A0). Higher amplitudes provide best phase noise,
whereas lower amplitudes save power.
Table 8
consumption, and the phase noise at 1 MHz.
Table 8.
PLL_A[1:0]
Calibrate the VCO at the desired frequency with an F
Set the A, B and R divider ratios for the desired F
gives the voltage swing level expected on the resonator nodes, the current
00
01
10
11
PFD
, follow the steps below:
VCO A performances versus amplitude setting (freq=3.3GHz)
1
Differential voltage swing
is still inside the nominal range.
PFD
to perform the calibration process is 1 MHz. When using a
(Vp)
1.1
1.3
1.9
2.1
LK
limit, without any external user command.
0
Current consumption
inside the operating temperature range
LK
PFD
MAX
(mA)
parameter reported in Table 5, that
16
18
27
30
.
PFD
=125; from -40 °C to +85 °C and
LK
less than 1 MHz.
parameter, provided that the
PN @1MHz (dBc/Hz)
-128.5
-125
-126
-129
STW81102

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