STW81102ATR STMicroelectronics, STW81102ATR Datasheet - Page 14
STW81102ATR
Manufacturer Part Number
STW81102ATR
Description
IC SYNTHESIZER MULTI RF 28VFQFPN
Manufacturer
STMicroelectronics
Type
Frequency Synthesizerr
Datasheet
1.STW81102AT.pdf
(53 pages)
Specifications of STW81102ATR
Pll
Yes
Input
Clock, Crystal
Output
Clock, Crystal
Number Of Circuits
1
Ratio - Input:output
3:2
Differential - Input:output
No/No
Frequency - Max
4.65GHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-VFQFN, 28-VFQFPN
Frequency-max
4.65GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STW81102ATR
Manufacturer:
ST
Quantity:
3 000
Electrical specifications
Table 6.
1. Phase noise SSB.
2. Normalized PN = Measured PN – 20log(N) – 10log(F
3. Typical phase noise at centre band frequency.
14/53
VCO A with divider by 2 (1500MHz-1810MHz) – open loop
Phase noise @ 1 kHz
Phase noise @ 10 kHz
Phase noise @ 100 kHz
Phase noise @ 1 MHz
Phase noise @ 10 MHz
Phase noise floor @ 40 MHz
VCO B with divider by 2 (2000MHz-2325MHz) – open loop
Phase noise @ 1 kHz
Phase noise @ 10 kHz
Phase noise @ 100 kHz
Phase noise @ 1 MHz
Phase noise @ 10 MHz
Phase noise floor @ 40 MHz
VCO A with divider by 4 (750MHz-905MHz) – open loop
Phase noise @ 1 kHz
Phase noise @ 10 kHz
Phase noise @ 100 kHz
Phase noise @ 1 MHz
Phase noise @ 10 MHz
Phase noise floor @ 40 MHz
VCO B with divider by 4 (1000MHz-1162.5MHz) – open loop
Phase noise @ 1 kHz
Phase noise @ 10 kHz
Phase noise @ 100 kHz
Phase noise @ 1 MHz
Phase noise @ 10 MHz
Phase noise floor @ 40 MHz
VCO amplitude setting to value [11].
All the closed-loop performances are specified using a reference clock signal at 76.8 MHz with phase noise of
-135dBc/Hz @1kHz offset, -145 dBc/Hz @10 kHz offset and -149.5dBc/Hz of noise floor.
comparison frequency at the PFD input.
Parameter
Phase noise specification (continued)
An evaluation kit is available upon request, including a powerful simulation tool
(STWPLLSim) that allows a very accurate estimation of the device’s phase noise according
to the desired project parameters (VCO frequency, selected output stage, reference clock,
frequency step, and so on); refer to
Test conditions
PFD
) where N is the VCO divider ratio (N=B*P+A) and F
Chapter 8: Application information
(3)
(3)
(3)
(3)
Min
-151.5
-151.5
-113
-135
-155
-112
-134
-155
-119
-141
-154
-155
-118
-140
-154
-155
Typ
-63
-90
-61
-89
-69
-96
-67
-95
for more details.
Max
PFD
STW81102
is the
dBc/Hz
dBc/Hz
dBc/Hz
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dBc/Hz
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dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Unit