ICS8633AF-01LFT IDT, Integrated Device Technology Inc, ICS8633AF-01LFT Datasheet - Page 6

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ICS8633AF-01LFT

Manufacturer Part Number
ICS8633AF-01LFT
Description
IC BUFFER ZD 1-3 LVPECL 28-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Distribution, Multiplexer , Zero Delay Bufferr
Datasheet

Specifications of ICS8633AF-01LFT

Pll
Yes with Bypass
Input
HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
LVPECL
Number Of Circuits
1
Ratio - Input:output
2:3
Differential - Input:output
Yes/Yes
Frequency - Max
700MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Frequency-max
700MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
8633AF-01LFT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS8633AF-01LFT
Manufacturer:
ICS
Quantity:
20 000
P
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8633-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10
capacitor should be connected to each V
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
8633AF-01
W
OWER
IRING THE
resistor along with a 10 F and a .01 F bypass
S
UPPLY
D
IFFERENTIAL
F
ILTERING
T
I
ECHNIQUES
NPUT TO
F
IGURE
Single Ended Clock Input
A
2. S
CCA
A
PPLICATION
CC
CCEPT
pin.
INGLE
, V
CCA
E
, and V
C1
0.1u
S
NDED
V_REF
INGLE
CC
www.idt.com
/2 is
S
CCO
IGNAL
E
6
I
NDED
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the
input clock swing is only 2.5V and V
1.25V and R2/R1 = 0.609.
D
1K
R1
1K
R2
RIVING
1-
VCC
L
TO
EVELS
D
nCLKx
CLKx
IFFERENTIAL
-3 D
F
IGURE
IFFERENTIAL
1. P
V
V
I
CCA
NPUT
CC
OWER
.01 F
S
.01 F
Z
UPPLY
-
CC
ERO
TO
ICS8633-01
3.3V
= 3.3V, V_REF should be
-3.3V LVPECL
F
10
10 F
ILTERING
D
ELAY
REV. B AUGUST 2, 2010
B
UFFER

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