MC88915FN55R2 IDT, Integrated Device Technology Inc, MC88915FN55R2 Datasheet - Page 9

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MC88915FN55R2

Manufacturer Part Number
MC88915FN55R2
Description
IC PLL CLOCK DRIVER 28-PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Driverr
Datasheet

Specifications of MC88915FN55R2

Pll
Yes with Bypass
Input
TTL
Output
CMOS, TTL
Number Of Circuits
1
Ratio - Input:output
2:8
Differential - Input:output
No/No
Frequency - Max
55MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-PLCC
Frequency-max
55MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
MC88915
LOW SKEW CMOS PLL CLOCK DRIVERS
TIMING NOTES:
1.
2.
The MC88915 aligns rising edges of the FEEDBACK
input and SYNC input; therefore, the SYNC input does
not require a 50% duty cycle.
All skew specs are measured between the VCC/2
crossing point of the appropriate output edges. All
skews are specified as “windows,” not as a ± deviation
around a center point.
2X_Q OUTPUT
SYNC INPUT
(SYNC[1] OR
Q/2 OUTPUT
Q5 OUTPUT
FEEDBACK
OUTPUTS
SYNC[0])
Q0–Q4
INPUT
t
SKEWALL
Figure 6. Output/Input Switching Waveforms and Timing Diagrams
(These waveforms represent the hook-up configuration of
t
PD
t
CYCLE
t
SKEWf
SYNC INPUT
9
3.
If a “Q” output is connected to the FEEDBACK input
(this situation is not shown), the “Q” output frequency
would match the SYNC input frequency, the 2X_Q
output would run at twice the SYNC frequency, and the
Q/2 output would run at half the SYNC frequency.
t
SKEWr
t
CYCLE
"Q" OUTPUTS
Figure
7a.)
t
SKEWf
MC88915 REV 6 JULY 10, 2007
t
SKEWr

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