MPC9774AE IDT, Integrated Device Technology Inc, MPC9774AE Datasheet - Page 8

• Manufacturer Part Number: MPC9774AE
• Description: IC PLL CLK GEN 1:14 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9774AE

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:14
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3V 1:14 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9774
3.3V 1:14 LVCMOS PLL Clock Generator
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to V
thus only a single terminated line can be driven by each
output of the MPC9774 clock driver. For the series
terminated case however there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 8 “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme
the fanout of the MPC9774 clock driver is effectively doubled
due to its capability to drive multiple lines.
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9774 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9774. The output waveform in Figure 9 “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
MPC9774
MOTOROLA
The MPC9774 clock driver was designed to drive high
This technique draws a fairly high level of DC current and
The waveform plots in Figure 9 “Single versus Dual Line
Figure 8. Single versus Dual Transmission Lines
Ω
Ω
CC
÷ 2.
Ω
Ω
Ω
Freescale Semiconductor, Inc.
For More Information On This Product,
Ω
Ω
Ω
Go to: www.freescale.com
8
8
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 10 “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is
perfectly matched.
At the load end the voltage will double, due to the near
Since this step is well above the threshold region it will not
Figure 10. Optimized Dual Line Termination
Figure 9. Single versus Dual Waveforms
Ω
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
V
Z
R
R
V
0
L
L
S
0
= V
= 50Ω || 50Ω
= 3.0 ( 25 ÷ (18 + 17 + 25)
= 1.31V
= 14Ω
= 36Ω || 36Ω
S
( Z
25Ω = 25Ω
0
÷ (R
Ω
Ω
S
+ R
0
+ Z
TIMING SOLUTIONS
Ω
Ω
0
))
NETCOM
MPC9774