MPC9772AE IDT, Integrated Device Technology Inc, MPC9772AE Datasheet - Page 11

• Manufacturer Part Number: MPC9772AE
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9772AE

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:18
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
Power Supply Filtering
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the V
characteristics, for instance I/O jitter. The MPC9772 provides
separate power supplies for the output buffers (V
phase-locked loop (V
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
V
power supply filter scheme. The MPC9772 frequency and
phase stability is most susceptible to noise with spectral
content in the 100 kHz to 20 MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop across the series filter resistor R
the I
pin) is typically 3 mA (5 mA maximum), assuming that a
minimum of 3.0 V must be maintained on the V
The resistor R
5-10 Ω to meet the voltage drop criteria.
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in
4.5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9772 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
CCA_PLL
The MPC9772 is a mixed analog/digital product. Its analog
The minimum values for R
As the noise frequency crosses the series resonant point
CC_PLL
V
CC
CC_PLL
Figure 7. V
pin for the MPC9772.
current (the current sourced through the V
F
Figure
power supply impacts the device
shown in
R
F
= 5–10Ω
R
CC_PLL
CC_PLL
7, the filter cut-off frequency is around
F
Figure 7
C
F
) of the device. The purpose of
F
33...100 nF
Power Supply Filter
and the filter capacitor C
C
Figure 7
F
10 nF
= 22 µF
must have a resistance of
F
. From the data sheet
illustrates a typical
V
V
CC_PLL
CC
MPC9772
CC_PLL
CC
) and the
CC_PLL
pin.
F
are
11
this section should be adequate to eliminate power supply
noise related problems in most designs.
Using the MPC9772 in Zero-Delay Applications
MPC9772. Designs using the MPC9772 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9772 clock driver allows for its use as a zero delay
buffer. The PLL aligns the feedback clock output edge with
the clock input reference edge resulting a near zero delay
through the device (the propagation delay through the device
is virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of Part-to-Part Skew
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9772 are connected together, the maximum overall
timing uncertainty from the common CCLKx input to any
output is:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Nested clock trees are typical applications for the
The MPC9772 zero delay buffer supports applications
This maximum timing uncertainty consist of 4 components:
CCLK
Any Q
Any Q
QFB
QFB
Max. skew
t
SK(PP)
Common
Device 1
Device 1
Device 2
Device2
= t
Figure 8. MPC9772 Maximum
(
∅
Device-to-Device Skew
)
+ t
t
SK(O)
JIT(∅)
+t
–t
SK(O)
(∅)
+ t
MPC9772 REV 6 FEBRUARY 7, 2007
PD, LINE(FB)
+t
(∅)
t
t
SK(PP)
JIT(∅)
+ t
t
+t
PD,LINE(FB)
JIT(
SK(O)
∅
)
⋅
CF