ICS932S422CFLF IDT, Integrated Device Technology Inc, ICS932S422CFLF Datasheet - Page 6

• Manufacturer Part Number: ICS932S422CFLF
• Description: IC PCIE GEN2 MAIN CLOCK 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of ICS932S422CFLF

• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output: -
• Input: -
• Other names: 932S422CFLF

1412A—12/10/07
1
1
2
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
Absolute Maximum Rating
Electrical Characteristics - Input/Supply/Common Output Parameters
Guaranteed by design and characterization, not 100% tested in production.
Guaranteed by design and characterization, not 100% tested in production.
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
Input ESD protection HBM
3.3V Core Supply Voltage
Operating Supply Current
Ambient Operating Temp
Low-level Output Voltage
3.3V Logic Input Supply
Modulation Frequency
Clock/Data Rise Time
Storage Temperature
Low Threshold Input-
Low Threshold Input-
Clock/Data Fall Time
Powerdown Current
Case Temperature
Input High Current
Input High Voltage
Input Low Current
Operating Current
Input Capacitance
Input Low Voltage
Current sinking at
Input Frequency
Clk Stabilization
Pin Inductance
SMBus Voltage
PARAMETER
PARAMETER
SCLK/SDATA
SCLK/SDATA
High Voltage
Low Voltage
Tdrive_PD
V
Integrated
Circuit
Systems, Inc.
Trise_PD
Tfall_PD
OL
Voltage
= 0.4 V
SYMBOL
Tambient
SYMBOL
ESD prot
VDD_In
VDD_A
Tcase
I
I
I
I
V
DD3.3OP
DD3.3OP
DD3.3PD
V
T
PULLUP
C
T
T
C
L
C
V
V
Ts
V
V
I
I
IH_FS
IL_FS
STAB
I
F
IL1
IL2
RI2C
FI2C
OUT
IH
pin
INX
DD
OL
IH
IL
IN
i
V
From VDD Power-Up or de-assertion
IN
V
= 0 V; Inputs with pull-up resistors
IN
all differential pairs tri-stated
Full Active, C
= 0 V; Inputs with no pull-up
CPU output enable after
Output pin capacitance
Triangular Modulation
(Max VIL - 0.15) to
(Min VIH + 0.15) to
all diff pairs driven
of PD to 1st clock
all outputs driven
PD de-assertion
(Min VIH + 0.15)
(Max VIL - 0.15)
CONDITIONS*
CONDITIONS
PD rise time of
PD fall time of
X1 & X2 pins
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
V
@ I
V
resistors
DD
IN
= 3.3 V
PULLUP
= V
-
-
-
-
-
-
L
= Full load;
DD
6
GND - 0.5
V
V
SS
SS
2000
MIN
-200
MIN
-65
0.7
2.7
30
-5
-5
0
2
4
- 0.3
- 0.3
14.31818
TYP
TYP
V
V
V
V
DD
DD
DD
DD
MAX
MAX
1000
0.35
150
115
350
400
300
300
0.8
1.8
+ 0.5V
+ 0.5V
70
5.5
0.4
70
12
33
+ 0.3
5
+ 0.3
7
5
6
5
5
5
ICS932S422C
UNITS
UNITS
MHz
kHz
mA
mA
mA
mA
ms
mA
°
°C
°C
uA
uA
uA
nH
pF
pF
pF
us
ns
ns
ns
ns
V
V
V
C
V
V
V
V
V
V
Notes
Notes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1