ICS951412AGLF IDT, Integrated Device Technology Inc, ICS951412AGLF Datasheet
ICS951412AGLF
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ICS951412AGLF Summary of contents
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Integrated Circuit Systems, Inc. System Clock Chip for ATI RS480 K8-based Systems Recommended Application: ATI RS480 systems using AMD K8 processors Output Features: • 14.318 MHz REF clocks • USB_48MHz USB clock • HyperTransport ...
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ICS951412A Pin Descriptions PIN PIN PIN NAME # TYPE Crystal input, Nominally 14.318MHz OUT Crystal output, Nominally 14.318MHz 3 VDD48 PWR Power pin for the 48MHz output.3.3V 4 USB_48MHz OUT 48.00MHz USB clock 5 GND ...
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Pin Descriptions (Continued) PIN PIN NAME Type # 29 ATIGCLKC0 OUT Complementary clock of differential SRC clock pair. 30 ATIGCLKT0 OUT True clock of differential SRC clock pair. 31 GNDATI PWR Ground for ATI Gclocks, nominal 3.3V 32 VDDATI PWR ...
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ICS951412A General Description The ICS951412A is a main clock synthesizer chip that provides all clocks required for ATI RS480-based systems. An SMBus interface allows full control of the device. Block Diagram X1 X2 FS(2:0) CLKREQA# CLKREQB# SEL75#/100 SDATA SCLK Skew ...
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General SMBus serial interface information How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS ...
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ICS951412A Table1: CPU Frequency Selection Table CPU CPU FS3 CPU CPU SS_EN (B0:b3) FS2 FS1 (B0:b4 ...
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Table2: SRC & ATIG Frequency Selection Table Byte 5 Bit4 Bit3 Bit2 Bit1 Bit0 SRC SRC SRC SRC SRC Spread FS3 FS2 FS1 FS0 Enable ...
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ICS951412A SMBus Table: Frequency Select Register Byte 0 Pin # Name - FS Source Bit 7 - CPU SS_EN Bit 6 Bit 5 - Reserved Bit 4 - CPU FS4 - CPU FS3 Bit 3 - CPU FS2 Bit 2 ...
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SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register Byte 3 Pin # Name 12,13 SRCCLK7 Bit 7 16,17 SRCCLK6 Bit 6 Bit 5 18,19 SRCCLK5 22,23 SRCCLK4 Bit 4 24,25 SRCCLK3 Bit 3 34,33 SRCCLK0 Bit 2 Bit 1 24,25 REQASRC3 ...
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ICS951412A SMBus Table: Device ID Register Byte 6 Pin # Name - DevID 7 Bit 7 - DevID 6 Bit 6 Bit 5 - DevID 5 Bit 4 - DevID 4 - DevID 3 Bit 3 - DevID 2 Bit ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V Logic Inputs . . . . . . . ...
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ICS951412A Electrical Characteristics - K8 Push Pull Differential Pair 70° 3.3 V +/-5 PARAMETER SYMBOL Rising Edge Rate V t Falling Edge Rate Differential Voltage DIFF Change in ...
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Electrical Characteristics - SRC 0.7V Current Mode Differential Pair 70° 3.3 V +/-5 PARAMETER SYMBOL Current Source Output Zo Impedance Voltage High VHigh Voltage Low VLow Max Voltage Vovs Min Voltage ...
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ICS951412A Electrical Characteristics - PCI33, HTT66 Clocks 70°C; VDD=3.3V +/-5 PARAMETER SYMBOL Long Accuracy ppm T PCI33 Clock period period T HTT66 Clock period period V Output High Voltage OH V Output Low Voltage ...
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Electrical Characteristics - 48MHz, USB 70° 3.3 V +/-5 PARAMETER SYMBOL Long Accuracy ppm T Clock period period V Output High Voltage OH V Output Low Voltage OL I Output High ...
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ICS951412A Electrical Characteristics - REF-14.318MHz 70° 3.3 V +/-5 PARAMETER SYMBOL Long Accuracy ppm T Clock period period Output High Voltage Output Low Voltage OL I Output High ...
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Common Recommendations for Differential Routing L1 length, Route as non L2 length, Route as non L3 length, Route as non Rs Rt Down Device Differential Routing L4 length, Route as coupled differential trace. L4 length, Route as coup differential trace. ...
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ICS951412A Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS951412 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on ...
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INDEX INDEX AREA AREA 45° 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C Ordering Information ICS951412AFLFT Example: ICS XXXX A F ...
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... ICS951412A INDEX INDEX AREA AREA Ordering Information ICS951412AGLFT Example: ICS XXXX 1231A—06/12/06 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP c SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS aaa VARIATIONS - SEATING SEATING 56 PLANE PLANE Reference Doc.: JEDEC Publication 95, MO-153 aaa C 10-0039 Designation for tape and reel packaging ...
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Revision History Rev. Issue Date Description A 6/12/2006 Initial Release 1231A—06/12/06 21 ICS951412A Page # - ...