IDT8737-11PGG8 IDT, Integrated Device Technology Inc, IDT8737-11PGG8 Datasheet - Page 9

• Manufacturer Part Number: IDT8737-11PGG8
• Description: IC CLK GEN DIFF-LVPECL 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of IDT8737-11PGG8

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8737-11PGG8

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS
bias resistors R1, R2, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to
position the V
R1 = 0.609.
TERMINATION FOR LVPECL OUTPUTS
ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal distortion. The diagrams below show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist. It is recommended that the board designers simulate to guarantee compatibility across all printed circuit and
clock component process variations.
APPLICATION INFORMATION
IDT8737-11
LOW SKEW, ÷ ÷ ÷ ÷ ÷ 1/÷ ÷ ÷ ÷ ÷ 2 DIFFERENTIAL-TO-3.3V LVPECL
R
The diagram below shows how the differential input can be wired to accept single-ended levels. The reference voltage V
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
F
TT
OUT
=
and xF
F
(V
OUT
OH
REF
+ V
OUT
OL
LVPECL Output Termination, layout A
in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V
are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to
1
/ V
DD
- 2) - 2
Zo = 50Ω
Zo = 50Ω
Zo
50Ω
CLK_IN
R
TT
Single-Ended Signal Driving Differential Input
50Ω
V
DD
0.1uF
F
C1
- 2V
IN
9
R2
R1
1K
1K
V
F
REF
OUT
V
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DD
+
-
LVPECL Output Termination, layout B
Zo = 50Ω
Zo = 50Ω
3
5
DD
2
2
Zo
Zo
= 3.3V, V
REF
3.3V
REF
∼
3
5
V
should be 1.25V and R2/
2
2
DD
Zo
Zo
/2 is generated by the
F
IN