MPC9351ACR2 IDT, Integrated Device Technology Inc, MPC9351ACR2 Datasheet - Page 5

• Manufacturer Part Number: MPC9351ACR2
• Description: IC PLL CLOCK DRIVER LV 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9351ACR2

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:9
• Differential - Input:output: Yes/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9351
Low Voltage PLL Clock Driver
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 7. DC Characteristics (V
Table 8. AC Characteristics (V
1. V
2. The MPC9351 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. V
Symbol
Symbol
V
V
t
t
t
t
JIT(PER)
PLZ, HZ
PZL, ZH
JIT(CC)
t
t
Z
f
CMR
CMR
I
I
f
f
t
JIT(∅)
V
C
and the input swing lies within the V
transmission line to a termination voltage of V
output.
refDC
LOCK
and the input swing lies within the V
V
V
V
V
C
CCQ
VCO
MAX
t
t
sk(o)
DC
t
BW
V
CCA
f
OUT
I
r
r
(∅)
ref
OH
IN
CMR
, t
, t
CMR
PP
OL
PD
PP
IH
IL
IN
f
f
(1)
(2)
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Common Mode Range
Output High Voltage
Output Low Voltage
Output Impedance
Input Leakage Current
Input Capacitance
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Input Frequency
VCO Frequency
Maximum Output Frequency
Reference Input Duty Cycle
Peak-to-Peak Input Voltage
Common Mode Range
TCLK Input Rise/Fall Time
Propagation Delay (static phase offset)
Output-to-Output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
PLL closed loop bandwidth
Cycle-to-cycle jitter
Single Output Frequency Configuration
Period Jitter
Single Output Frequency Configuration
I/O Phase Jitter
Maximum PLL Lock Time
Characteristics
Characteristics
CC
CC
= 2.5 V ± 5%, T
= 2.5 V ± 5%, T
PP
PP
PCLK to EXT_FB
TCLK to EXT_FB
100 – 200 MHz
(DC) specification.
(AC) specification. Violation of V
50 – 100 MHz
PCLK, PCLK
PCLK, PCLK
PCLK, PCLK
PCLK, PCLK
÷ 2 feedback
÷ 4 feedback
÷ 8 feedback
25 – 50 MHz
÷ 2 feedback
÷ 4 feedback
÷ 8 feedback
÷ 4 feedback
÷ 4 feedback
÷ 2 output
÷ 4 output
÷ 8 output
TT
. Alternatively, the device drives up to two 50 Ω series terminated transmission lines per
A
A
= -40° to 85°C)
= -40° to 85°C)
48.75
–100
47.5
Min
Min
250
100
200
100
500
1.7
1.0
1.8
1.2
0.1
50
25
50
25
25
45
0
5
TT.
CMR
(1)
4.0 – 15.0
2.0 – 7.0
0.7 – 2.0
6.0 – 25
17 – 20
Typ
Typ
or V
4.0
3.0
8.0
10
50
50
50
10
PP
impacts static phase offset t
V
V
V
CC
CC
CC
51.75
±200
1000
+100
+300
Max
Max
52.5
200
100
400
200
100
150
0.7
0.6
5.0
1.0
1.0
1.0
1.0
50
50
75
55
12
12
22
15
+ 0.3
– 0.6
– 0.6
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
mV
mA
mA
mV
µA
ms
pF
pF
%
ns
ps
ps
ps
%
%
%
ns
ns
ns
ps
ps
ps
Ω
V
V
V
V
V
V
LVCMOS
LVCMOS
LVPECL
LVPECL
I
I
V
Per Output
V
All V
LVPECL
LVPECL
0.7 to 1.7 V
0.6 to 1.8 V
–3 dB point of PLL transfer
characteristic
RMS value
RMS value
RMS value
OH
OL
PLL locked
PLL locked
(∅)
IN
CCA
= 15 mA
= –15 mA
= V
.
CC
Pin
CC
Pins
Condition
Condition
or GND
(2)
CMR
CMR
MPC9351
range
range
NETCOM
MPC9351
5