MPC9653AACR2/W IDT, Integrated Device Technology Inc, MPC9653AACR2/W Datasheet - Page 5

• Manufacturer Part Number: MPC9653AACR2/W
• Description: IC PLL CLK GEN 1:8 3.3V 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9653AACR2/W

• Pll: Yes with Bypass
• Input: LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: Yes/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
Table 6. AC Characteristics (V
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. ÷ 4 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE = 0.
3. ÷ 8 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE = 0.
4. In bypass mode, the MPC9653A divides the input reference clock.
5. The input frequency f
6. f
7. f
8. V
9. Calculation of reference duty cycle limits: DC
10. Valid for f
11. Refer to the Application Information section for part-to-part skew calculation in PLL zero-delay mode.
12. For a specified temperature and voltage, includes output skew.
13. I/O phase jitter is reference frequency dependent. Refer to
14. –3 dB point of PLL transfer characteristics.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Symbol
t
f
t
t
t
t
V
PW, MIN
JIT(PER)
VCOlock
t
PLZ, HZ
PZL, LZ
t
input swing lies within the V
For example, at f
JIT(CC)
t
t
sk(PP)
t
VCO
VCOlock
f
f
JIT(∅)
f
LOCK
V
CMR
sk(O)
R
BW
VCO
MAX
t
DC
REF
t
CMR
(∅)
PD
, t
PP
F
is frequency range where AC parameters are guaranteed.
8
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
is frequency range that the PLL guaranteed to lock, AC parameters only guaranteed over f
REF
Input Reference Frequency
PLL Mode, External Feedback
VCO Operating Frequency Range
VCO Lock Frequency Range
Output Frequency
Peak-to-Peak Input Voltage
Common Mode Range
Input Reference Pulse Width
Propagation Delay (static phase offset)
Propagation Delay
Output-to-Output Skew
Device-to-Device Skew in PLL and Divider Bypass
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-Cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidth
PLL mode, external feedback
Maximum PLL Lock Time
= 50 MHz and FB = ÷ 8 (VCO_SEL = 1). For other reference frequencies: t
PLL and divider bypass (BYPASS = 0), PCLK to Q0–7
PLL disable (BYPASS = 1 and PLL_EN = 0), PCLK to Q0–7
REF
REF
= 100 MHz the input duty cycle range is 20% < DC < 80%.
must match the VCO frequency range divided by the feedback divider ratio FB: f
Input reference frequency in PLL bypass mode
13
PP
(AC) specification. Violation of V
CC
11
Characteristics
= 3.3 V ± 5%, T
14
9
7
REF,MIN
5, 6
10
= t
A
= 0°C to 70°C)
PW,MIN
APPLICATIONS INFORMATION
PCLK to FB_IN
÷ 4 feedback
÷ 8 feedback
÷ 4 feedback
÷ 8 feedback
÷ 4 feedback
÷ 8 feedback
12
⋅ f
CMR
REF
RMS (1σ)
TT
or V
PCLK
PCLK
.
⋅ 100% and DC
5
1
PP
2
3
4
2
3
2
3
impacts static phase offset t
Min
200
145
450
–75
1.2
1.2
3.0
0.1
50
25
50
25
45
0
2
REF,MAX
(∅)
[ps] = 50 ps ± (1 ÷ (120 ⋅ f
section for details.
= 100% - DC
Typ
50
VCO
.
(∅)
V
0.5 – 1.3
REF
.
CC
REF,MIN
0.8 – 4
1000
Max
62.5
62.5
125
200
500
500
125
125
150
100
100
3.3
7.0
1.5
1.0
7.0
6.0
55
25
10
– 0.75
= f
VCO
.
÷ FB.
REF
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
mV
ms
ns
ps
ns
ns
ps
ns
ns
ns
ns
ps
ps
ps
%
V
)).
CMR
MPC9653A
PLL locked
PLL locked
PLL locked
PLL locked
LVPECL
LVPECL
PLL locked
BYPASS = 0
PLL locked
0.55 to 2.4 V
range and the
Condition
NETCOM
MPC9653A
533