MPC9653AAC/W IDT, Integrated Device Technology Inc, MPC9653AAC/W Datasheet - Page 3

• Manufacturer Part Number: MPC9653AAC/W
• Description: IC PLL CLK GEN 1:8 3.3V 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9653AAC/W

• Pll: Yes with Bypass
• Input: LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: Yes/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
Table 1. Pin Configuration
Table 2. Function Table
1. PLL operation requires BYPASS = 1 and PLL_EN = 1.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
PCLK, PCLK
FB_IN
VCO_SEL
BYPASS
PLL_EN
MR/OE
Q0–7
QFB
GND
V
V
PLL_EN
BYPASS
VCO_SEL
MR/OE
CC_PLL
CC
Control
Pin
Default
Input
Input
Input
Input
Input
Input
Output
Output
Supply
Supply
Supply
1
1
1
0
I/O
Test mode with PLL bypassed. The reference clock (PCLK) is
substituted for the internal VCO output. MPC9653A is fully
static and no minimum frequency limit applies. All PLL related
AC characteristics are not applicable.
Test mode with PLL and output dividers bypassed. The
reference clock (PCLK) is directly routed to the outputs.
MPC9653A is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not applicable.
VCO ÷ 1 (High frequency range). f
Outputs enabled (active)
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
V
CC
CC
Type
PECL reference clock signal
PLL feedback signal input, connect to QFB
Operating frequency range select
PLL and output divider bypass select
PLL enable/disable
Output enable/disable (high-impedance tristate) and device reset
Clock outputs
Clock output for PLL feedback, connect to FB_IN
Negative power supply (GND)
PLL positive power supply (analog power supply). It is recommended to use an external RC filter for
the analog power supply pin V
Positive power supply for I/O and core. All V
for correct operation
0
REF
= f
Q0–7
= 4 ⋅ f
3
CC_PLL
VCO
. Refer to
Selects the VCO output
Selects the output dividers.
VCO ÷ 2 (Low output range). f
Outputs disabled (high-impedance state) and reset of the
device. During reset the PLL feedback loop is open. The
VCO is tied to its lowest frequency. The length of the reset
pulse should be greater than one reference clock cycle
(PCLK).
CC
Function
APPLICATIONS INFORMATION
pins must be connected to the positive power supply
1
1
REF
= f
for details.
Q0–7
MPC9653A
= 8 ⋅ f
VCO
NETCOM
MPC9653A
531