ICS9112AM-17 IDT, Integrated Device Technology Inc, ICS9112AM-17 Datasheet

ICS9112AM-17

Manufacturer Part Number

ICS9112AM-17

Description

IC BUFFER HI PERFORMANCE 16-SOIC

Manufacturer

IDT, Integrated Device Technology Inc

Type

Zero Delay Bufferr

Datasheet

1.ICS9112BF-17LFT.pdf (8 pages)

Specifications of ICS9112AM-17

Pll

Yes

Input

Clock

Output

Clock

Number Of Circuits

Ratio - Input:output

1:9

Differential - Input:output

No/No

Frequency - Max

133MHz

Divider/multiplier

No/No

Voltage - Supply

2.97 V ~ 5.5 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

16-SOIC

Frequency-max

133MHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

9112AM-17

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Low Skew Output Buffer

General Description

The ICS9112-17 is a high performance, low skew, low jitter

zero delay buffer. It uses a phase lock loop (PLL)

technology to align, in both phase and frequency, the REF

input with the CLKOUT signal. It is designed to distribute

high speed clocks in PC systems operating at speeds

from 25 to 133 MHz.

ICS9112-17 is a zero delay buffer that provides

synchronization between the input and output. The

synchronization is established via CLKOUT feed back to

the input of the PLL. Since the skew between the input and

output is less than +/- 350 pS, the part acts as a zero delay

buffer.

The ICS9112-17 has two banks of four outputs controlled

by two address lines. Depending on the selected address

line, bank B or both banks can be put in a tri-state mode.

In this mode, the PLL is still running and only the output

buffers are put in a high impedance mode. The test mode

shuts off the PLL and connects the input directly to the

output buffers (see table below for functionality).

The ICS9112-17 comes in a sixteen pin 150 mil SOIC or

16 pin SSOP package. In the absence of REF input, will

be in the power down mode. In this mode, the PLL is turned

off and the output buffers are pulled low. Power down mode

provides the lowest power consumption for a standby

condition.

Block Diagram

0051K—11/02/04

Integrated

Circuit

Systems, Inc.

Functionality

Features

•

Zero input - output delay

Frequency range 25 - 133 MHz (3.3V)

High loop filter bandwidth ideal for Spread Spectrum

applications.

Less than 200 ps cycle to cycle Jitter

Skew controlled outputs

Skew less than 250 ps between outputs

Available in 16 pin, 150 mil SSOP & SOIC package

r T

Pin Configuration

(

16 pin SSOP & SOIC

, 1

s i

i r

a t

e v

) 4

s s

e t

r T

(

, 1

s i

i r

e v

a t

) 4

s s

e t

i r

e v

s s

ICS9112-17

p t

c r

t u

d t

Related parts for ICS9112AM-17

ICS9112AM-17 Summary of contents

Page 1

Integrated Circuit Systems, Inc. Low Skew Output Buffer General Description The ICS9112- high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF ...

Page 2

ICS9112-17 Pin Descriptions ...

Page 3

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . ...

Page 4

ICS9112-17 Electrical Characteristics - OUTPUT 70° 5.0 V +/-10 DDL PARAMETER SYMBOL Output Impedance R DSP Output Impedance R DSN Output High Voltage V OH Output Low Voltage V ...

Page 5

Output to Output Skew The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all ...

Page 6

ICS9112-17 Application Suggestion: ICS9112- mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise generated by charging or discharging of internal or external capacitor on the power supply pins. This type of ...

Page 7

VARIATIONS Reference Doc.: JEDEC Publication 95, MO-137 10-0032 Ordering Information 9112yF-17LF-T Example: XXXX y F PPP Lx- T 0051K—11/02/04 SYMBOL mm. N MIN MAX 16 4.80 5.00 ...

Page 8

ICS9112-17 N INDEX INDEX AREA AREA 45° 45° Ordering Information 9112yM-17LF-T Example: XXXX y M PPP Lx- T 0051K—11/02/04 C SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS ...

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