MK1413STR IDT, Integrated Device Technology Inc, MK1413STR Datasheet - Page 3

• Manufacturer Part Number: MK1413STR
• Description: IC AUDIO CLK SOURCE MPEG 8-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Synthesizer - Audior

Specifications of MK1413STR

• Pll: Yes
• Input: Clock, Crystal
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 16.9344MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Frequency-max: 16.9344MHz
• Number Of Outputs: 1
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Information
Series Termination Resistor
Clock output traces should use series termination. For
series terminating a 50 trace (a commonly used trace
impedance), place a 33 resistor in series with the clock line
and as close to the clock output pin as possible. The
nominal impedance of the clock output is 20 .
Crystal Load Capacitors
The device crystal connections should include pads for
capacitors from X1 to ground and from X2 to ground, and a
parallel rsonant 14.31818 MHz crystal is recommended.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. To reduce possible noise pickup, use very
short PCB traces (and no vias) been the crystal and device.
The value (in pF) of each crystal load capacitor should equal
(C
capacitance in pF. The frequency tolerance of the crystal
should be 50 ppm or better.For a clock input, connect X1
and leave X2 unconnected. Because these capacitors
adjust the stray capacitance of the PCB, check the output
frequency using your final layout to see if the value of C
should be changed.
PCB Layout Recommendations
Observe the following guidelines for optimum device
IDT™ / ICS™ MPEG AUDIO CLOCK SOURCE
MK1413
MPEG AUDIO CLOCK SOURCE
L
-4) x2, where C
L
is the crystal’s load (correlation)
3
performance and lowest output phase noise:
1) Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted next to the device
with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, and obtain the best signal integrity, the
33 series termination resistor should be placed close to
the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the MK1413. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
MK1413
CLOCK SYNTHESIZER
REV G 051310