ICS9112AM-16T IDT, Integrated Device Technology Inc, ICS9112AM-16T Datasheet
ICS9112AM-16T
Specifications of ICS9112AM-16T
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ICS9112AM-16T Summary of contents
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Integrated Circuit Systems, Inc. Low Skew Output Buffer General Description The ICS9112A- high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input ...
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ICS9112A-16 Pin Descriptions ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . ...
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ICS9112A-16 Switching Characteristics ...
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Output to Output Skew The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all ...
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... ICS9112A-16 N INDE X ARE 45° 150 mil (Narrow Body) SOIC Ordering Information ICS9112AM-16LF-T Example: ICS XXXX A M PPP LF-T 1337K—08/03/07 C SYMBOL COMMON DIMENSIONS α a VARIATIONS N SEA TING 8 PLANE Reference Doc.: JEDEC Publication 95, MS-012 .10 (.004) 10-0030 Designation for tape and reel packaging ...
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INDEX AREA aaa 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information 9112AG-16LF-T Example: XXXX A G PPP LF-T 1337K—08/03/07 SYMBOL ...
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ICS9112A-16 Revision History Rev. Issue Date Description H 09/01/04 Updated Lead Free information I 11/02/04 Added LN option J 04/26/07 Removed LN option superceded by LF. K 08/03/07 Updated Switching Characteristics Rise/Fall time. 1337K—08/03/07 8 Page # 6-7 6-7 6-7 ...